Florian Schraut

Publication Activity (10 Years)

Years Active: 2017-2023
Publications (10 Years): 7

Top Topics

Design Considerations

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Heiner Bauer, Marco Stolba, Stefan Scholze, Dennis Walter, Christian Mayr, Alexander Oefelein, Sebastian Höppner, André Scharfe, Florian Schraut, Holger Eisenreich
A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. CoRR (2023)
Heiner Bauer, Marco Stolba, Stefan Scholze, Dennis Walter, Christian Mayr, Alexander Oefelein, Sebastian Höppner, André Scharfe, Florian Schraut, Holger Eisenreich
A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. ISOCC (2023)
Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Heiner Bauer, Farkas Csaszar, Robert Niebsch, Jörg Schreiter, Holger Eisenreich, Sebastian Höppner
A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. COOL CHIPS (2020)
Sebastian Höppner, Holger Eisenreich, Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Jörg Schreiter, Thorsten Riedel, Heiner Bauer, Robert Niebsch, Stephan Scherzer, Thomas Hocker, Stefan Scholze, Stephan Henker, Matthias Nossmann, Ulrich Hensel, Helmut Prengel
Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology. IEEE Trans. Circuits Syst. II Express Briefs (10) (2020)
Florian Schraut, Holger Eisenreich, Sebastian Höppner, Christian Mayr
A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology. ISCAS (2019)
Sebastian Höppner, Jörg Schreiter, Robert Niebsch, Stephan Scherzer, Ulrich Hensel, Jörg Winkler, Mario Orgis, Holger Eisenreich, Dennis Walter, Uwe Steeb, André Scharfe, Clifford Dmello, Robert Sinkwitz, Heiner Bauer, Alexander Oefelein, Florian Schraut
How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC. ESSDERC (2019)
Heiner Bauer, Sebastian Höppner, Johannes Partzsch, Dennis Walter, Christian Mayr, Florian Schraut, Holger Eisenreich
Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology. NORCAS (2017)