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A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology.
Florian Schraut
Holger Eisenreich
Sebastian Höppner
Christian Mayr
Published in:
ISCAS (2019)
Keyphrases
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cmos technology
low voltage
low power
high speed
power consumption
parallel processing
user friendly
power line
random access memory
design considerations
silicon on insulator
low cost
cost effective
power management
power dissipation
data center
leakage current
real time