John Bainbridge

Publication Activity (10 Years)

Years Active: 1990-2011
Publications (10 Years): 0

Publications

Luis A. Plana, David M. Clark, Simon Davidson, Steve B. Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. ACM J. Emerg. Technol. Comput. Syst. 7 (4) (2011)
Luis A. Plana, John Bainbridge, Steve B. Furber, Sean Salisbury, Yebin Shi, Jian Wu
An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. NOCS (2008)
Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley
Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus. ASYNC (2007)
Steve B. Furber, John Bainbridge
Future Trends in SoC Interconnect. SoC (2005)
Aristides Efthymiou, John Bainbridge, Douglas A. Edwards
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Trans. Very Large Scale Integr. Syst. 13 (12) (2005)
Aristides Efthymiou, John Bainbridge, Douglas A. Edwards
Adding Testability to an Asynchronous Interconnect for GALS SoC. Asian Test Symposium (2004)
Stephen B. Furber, John Bainbridge, J. Mike Cumpstey, Steve Temple
codes. Neural Networks 17 (10) (2004)
John Bainbridge, Stephen B. Furber
Chain: A Delay-Insensitive Chip Area Interconnect. IEEE Micro 22 (5) (2002)
John Bainbridge
Defining Testability Metrics Axiomatically. Softw. Test. Verification Reliab. 4 (2) (1994)
John Bainbridge
A Heuristic Method for Generating Large Random Expressions. Inf. Process. Lett. 44 (3) (1992)
John Bainbridge, Robin W. Whitty, John Wordsworth
Obtaining Structural Metrics of Z Specifications for Systems Development. Z User Workshop (1990)