Chain: A Delay-Insensitive Chip Area Interconnect.

John Bainbridge Stephen B. Furber

Published in: IEEE Micro (2002)

Keyphrases

delay insensitive
high speed
low power
power dissipation
asynchronous circuits
low cost
single chip
power consumption
analog vlsi
chip design
cmos technology
high density
physical design
programmable logic
neural network
image sensor
data sets