Aristides Efthymiou

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 4

Top Topics

Variable Length

Reduced Complexity

Adaptive Thresholding

Top Venues

Publications

Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas
Deep Learning Based Detection of Anti-Reflective Obstacles in VLC Systems. ICAIIC (2024)
Ioannis Rizos, Georgios Papatheodorou, Aristides Efthymiou
Exploring the Design Space of 32x32 Approximate Reduced Complexity Wallace Multipliers. MOCAST (2024)
Christoforos Papaioannou, Marina E. Plissiti, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas
Signal decoding in an NLOS VLC system with the presence of anti-reflective obstacles. BlackSeaCom (2022)
Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas
An efficient adaptive thresholding scheme for signal decoding in NLOS VLC systems. MeditCom (2021)
Aristides Efthymiou
An error tolerant CAM with nand match-line organization. ACM Great Lakes Symposium on VLSI (2013)
Aristides Efthymiou
Initialization-Based Test Pattern Generation for Asynchronous Circuits. IEEE Trans. Very Large Scale Integr. Syst. 18 (4) (2010)
Phillip David Ferguson, Aristides Efthymiou, Tughrul Arslan, Danny Hume
Optimising Self-Timed FPGA Circuits. DSD (2010)
Dilip P. Vasudevan, Aristides Efthymiou
A Partial Scan Based Test Generation for Asynchronous Circuits. DDECS (2008)
Rahman Hassan, Antony Harris, Nigel P. Topham, Aristides Efthymiou
Synthetic Trace-Driven Simulation of Cache Memory. AINA Workshops (1) (2007)
Aristides Efthymiou
Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits. DDECS (2007)
Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou
Fast, Parallel Two-Rail Code Checker with Enhanced Testability. IOLTS (2005)
Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou
A Low-Power Processor Architecture Optimized forWireless Devices. ASAP (2005)
Aristides Efthymiou, John Bainbridge, Douglas A. Edwards
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Trans. Very Large Scale Integr. Syst. 13 (12) (2005)
Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. ASYNC (2004)
Aristides Efthymiou, Jim D. Garside
A CAM with mixed serial-parallel comparison for use in low energy caches. IEEE Trans. Very Large Scale Integr. Syst. 12 (3) (2004)
Aristides Efthymiou, John Bainbridge, Douglas A. Edwards
Adding Testability to an Asynchronous Interconnect for GALS SoC. Asian Test Symposium (2004)
Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards
Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. DATE (2004)
Aristides Efthymiou, Jim D. Garside
Adaptive Pipeline Structures fo Speculation Control. ASYNC (2003)
Aristides Efthymiou, Jim D. Garside
An adaptive serial-parallel CAM architecture for low-power cache blocks. ISLPED (2002)
Aristides Efthymiou, Jim D. Garside
Adaptive Pipeline Depth Control for Processor Power-Management. ICCD (2002)
Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple
Power Management in the Amulet Microprocessors. IEEE Des. Test Comput. 18 (2) (2001)
Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou
Pipelined Memory Shared Buffer for VLSI Switches. SIGCOMM (1995)