Angela Arapoyanni

Publication Activity (10 Years)

Years Active: 1999-2016
Publications (10 Years): 7

Top Topics

Error Tolerance

Integrated Circuit

Top Venues

Panhellenic Conference on Informatics

IEEE Trans. Computers

Publications

Stefanos Valadimas, Angela Arapoyanni, Yiorgos Tsiatouhas
Timing error mitigation in microprocessor cores. ICECS (2016)
Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni
Timing Error Tolerance in Small Core Designs for SoC Applications. IEEE Trans. Computers 65 (2) (2016)
Helen-Maria Dounavi, Yiorgos Tsiatouhas, Angela Arapoyanni
Scan chain based at-speed diagnosis in the presence of scan output compaction schemes. Panhellenic Conference on Informatics (2015)
Anthi Anastasiou, Yiorgos Tsiatouhas, Angela Arapoyanni
On the reuse of existing error tolerance circuitry for low power scan testing. ISCAS (2015)
Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
testing in digital integrated circuits. Integr. 50 (2015)
John Liaperdos, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Yiorgos Tsiatouhas, Angela Arapoyanni, Xin Li
Fast deployment of alternate analog test using Bayesian model fusion. DATE (2015)
John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas
A method for the estimation of defect detection probability of analog/RF defect-oriented tests. DATE (2015)
Stefanos Valadimas, Angela Arapoyanni
Timing Error Tolerance in Pipeline Based Core Designs. Panhellenic Conference on Informatics (2014)
Stefanos Valadimas, Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Xrysovalantis Kavousianos
The Time Dilation Technique for Timing Error Tolerance. IEEE Trans. Computers 63 (5) (2014)
John Liaperdos, Angela Arapoyanni, Y. Tsiatouhas
Adjustable RF Mixers' Alternate Test Efficiency Optimization by the Reduction of Test Observables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (9) (2013)
Katerina Katsarou, Yiorgos Tsiatouhas, Angela Arapoyanni
NBTI aging tolerance in pipeline based designs NBTI. IOLTS (2013)
Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Petros Xarchakos
Effective Timing Error Tolerance in Flip-Flop Based Core Designs. J. Electron. Test. 29 (6) (2013)
John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas
A Built-In Voltage Measurement Technique for the Calibration of RF Mixers. IEEE Trans. Instrum. Meas. 62 (4) (2013)
Lampros Dermentzoglou, John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas
Testing wireless transceivers' RF front-ends utilizing defect-oriented BIST techniques. ICECS (2012)
Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Adrian Evans
Single event upset tolerance in flip-flop based microprocessor cores. DFT (2012)
Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni
Cost and power efficient timing error tolerance in flip-flop based microprocessor cores. ETS (2012)
Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni
Timing error tolerance in nanometer ICs. IOLTS (2010)
Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas
A Build-In Self-Test technique for RF Mixers. DDECS (2010)
Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas
A Built-In-Test Circuit for RF Differential Low Noise Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni
A Current Mode, Parallel, Two-Rail Code Checker. IEEE Trans. Computers 57 (8) (2008)
Yiorgos Tsiatouhas, Angela Arapoyanni, Dionisis Skias
A Scan Flip-Flop for Low-Power Scan Operation. ICECS (2007)
Konstantinos Limniotis, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni
A Design Technique for Energy Reduction in NORA CMOS Logic. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2006)
Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism. ICECS (2006)
Y. Tsiatouhas, Angela Arapoyanni
High fan-in differential current mirror logic. ISCAS (2006)
Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou
Fast, Parallel Two-Rail Code Checker with Enhanced Testability. IOLTS (2005)
Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
An embedded IDDQ testing circuit and technique. ICECS (2005)
Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir
testing circuit. ESSCIRC (2005)
Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni
A Built-In Self-Test Scheme for Differential Ring Oscillators. ISQED (2005)
Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni
Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications . ISVLSI (2004)
Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs. J. Electron. Test. 20 (5) (2004)
Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators. J. Electron. Test. 20 (2) (2004)
Yiorgos Tsiatouhas, Konstantinos Limniotis, Angela Arapoyanni, Themistoklis Haniotakis
A low power NORA circuit design technique based on charge recycling. ICECS (2003)
Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni
An Embedded IDDQ Testing Architecture and Technique. ISQED (2003)
Christos Kokozidis, Stamatis Bouras, Angela Arapoyanni
Building blocks for a 100 MS/s, 10-b, 1.8 V CMOS cascaded folding & interpolating A/D converter. ICECS (2003)
Y. Tsiatouhas, Sotirios Matakias, Angela Arapoyanni, Th. Haniotakis
A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs. IOLTS (2003)
Lampros Dermentzoglou, Yiorgos Tsiatouhas, Angela Arapoyanni
A novel scheme for testing radio frequency voltage controlled oscillators. ICECS (2003)
Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
A new technique for IDDQ testing in nanometer technologies. Integr. 31 (2) (2002)
Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni
Charge Pump Circuits for Low-voltage Applications. VLSI Design 2002 (1) (2002)
Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. IOLTW (2002)
A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology. ISCAS (5) (2002)
Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
Extending the Viability of IDDQ Testing in the Deep Submicron Era. ISQED (2002)
Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni, Lampros Dermentzoglou
A high-performance low-power static differential double edge-triggered flip-flop. ISCAS (4) (2001)
A. Chrisanthopoulos, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni
New test pattern generation units for NPSF oriented memory built-in self test. ICECS (2001)
A. Chrisanthopoulos, Yiannis Moisiadis, A. Varagis, Y. Tsiatouhas, Angela Arapoyanni
A new flash memory sense amplifier in 0.18 μm CMOS technology. ICECS (2001)
Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni
A CMOS differential logic for low-power and high-speed applications. ISCAS (4) (2001)
Lampros Dermentzoglou, George Kamoulakos, Angela Arapoyanni
A 0.35 μm SiGe BiCMOS front end for GSM low IF cellular receiver applications. ICECS (2001)
Dionisis Skias, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni
A state assignment algorithm for finite state machines. ICECS (2000)
George Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni
Management of charge pump circuits. Integr. 30 (1) (2000)
A. Chrisanthopoulos, George Kamoulakos, Y. Tsiatouhas, Angela Arapoyanni
A test pattern generation unit for memory NPSF built-in self test. ICECS (2000)
Ilias Bouras, Yiannis Liaperdos, Angela Arapoyanni
A high speed low power CMOS clock driver using charge recycling technique. ISCAS (2000)
Lampros Dermentzoglou, Aristodimos Pneumatikakis, Angela Arapoyanni, Yiannis Moisiadis
A multimode extra high IF1 image rejection receiver for TDMA applications. ICECS (2000)
Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni
A CMOS charge pump for low voltage operation. ISCAS (2000)
Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos
A Versatile Built-In Self-Test Scheme for Delay Fault Testing. DATE (2000)
Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni
High performance level restoration circuits for low-power reduced-swing interconnect schemes. ICECS (2000)
Ioannis Moisiadis, Ilias Bouras, Constantin Papadas, Angela Arapoyanni
Performance comparison of driver architectures in submicron CMOS and BiCMOS technologies for low voltage operation. ICECS (1999)
Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni
Novel domino logic designs. ICECS (1999)