Guillaume Prenat

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 29

Top Topics

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. ETS (2024)
Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations. DATE (2024)
Soyed Tuhin Ahmed, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. CoRR (2024)
Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations. CoRR (2024)
Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI. CoRR (2024)
Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI. DATE (2024)
Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Spatial-SpinDrop: Spatial Dropout-based Binary Bayesian Neural Network with Spintronics Implementation. CoRR (2023)
Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Scale-Dropout: Estimating Uncertainty in Deep Neural Networks Using Stochastic Scale. CoRR (2023)
Ghislain Takam Tchendjou, Kamal Danouchi, Guillaume Prenat, Lorena Anghel
Spintronic Memristor-Based Binarized Ensemble Convolutional Neural Network Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (6) (2023)
Kamal Danouchi, Guillaume Prenat, Philippe Talatchian, Louis Hutin, Lorena Anghel
Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits. ISVLSI (2023)
Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation. DATE (2023)
Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
SpinDrop: Dropout-Based Bayesian Binary Neural Networks With Spintronic Implementation. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (1) (2023)
Joao Henrique Quintino Palhares, Yann Beilliard, Jury Sandrini, Franck Arnaud, Kevin Garello, Guillaume Prenat, Lorena Anghel, Fabien Alibart, Dominique Drouin, Philippe Galy
A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses. CoRR (2023)
Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures. ACM Trans. Embed. Comput. Syst. 22 (5s) (2023)
Kamal Danouchi, Guillaume Prenat, Lorena Anghel
Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network. LATS (2022)
Etienne Becle, Guillaume Prenat, Philippe Talatchian, Lorena Anghel, Ioan Lucian Prejbeanu
A Fast, Energy Efficient and Tunable Magnetic Tunnel Junction Based Bitstream Generator for Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (8) (2022)
Theo Soriano, David Novo, Guillaume Prenat, Gregory di Pendina, Pascal Benoit
MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge. VLSI-SoC (2022)
Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices. NANOARCH (2022)
Etienne Becle, Philippe Talatchian, Guillaume Prenat, Lorena Anghel, Ioan Lucian Prejbeanu
Fast Behavioral VerilogA Compact Model for Stochastic MTJ. ESSDERC (2021)
Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Lionel Torres, Sophiane Senni, Guillaume Patrigeon, Pascal Benoit, Gregory di Pendina, Guillaume Prenat
A Universal Spintronic Technology based on Multifunctional Standardized Stack. DATE (2020)
Guillaume Patrigeon, Pascal Benoit, Lionel Torres, Sophiane Senni, Guillaume Prenat, Gregory di Pendina
Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power Microcontrollers. IEEE Access 7 (2019)
Mounia Kharbouche-Harrari, Rana Alhalabi, Jérémy Postel-Pellerin, Romain Wacquez, Driss Aboulkassimi, Etienne Nowak, Ioan Lucian Prejbeanu, Guillaume Prenat, Gregory di Pendina
MRAM: from STT to SOT, for security and memory. DCIS (2018)
Elena Ioana Vatajelu, Lorena Anghel, Jean-Michel Portal, Marc Bocquet, Guillaume Prenat
Resistive and Spintronic RAMs: Device, Simulation, and Applications. IOLTS (2018)
Sophiane Senni, Frederic Ouattara, Jad Mohdad, Kaan Sevin, Guillaume Patrigeon, Pascal Benoit, Pascal Nouet, Lionel Torres, François Duhem, Gregory di Pendina, Guillaume Prenat
From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip. VLSI-SoC (2018)
Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Abdoulaye Gamatié, Pascal Nouet, Frederic Ouattara, Gilles Sassatelli, Kotb Jabeur, Pierre Vanhauwaert, A. Atitoaie, I. Firastrau, Gregory di Pendina, Guillaume Prenat
Using multifunctional standardized stack as universal spintronic technology for IoT. DATE (2018)
Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Pascal Nouet, Rui Ma, Martin Kreißig, Frank Ellinger, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Guillaume Prenat
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack. ISVLSI (2017)
Guillaume Prenat, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Fabian Oboril, Rajendra Bishnoi, Mojtaba Ebrahimi, Nathalie Lamard, Olivier Boulle, Kevin Garello, Juergen Langer, Berthold Ocker, Marie-Claire Cyrille, Pietro Gambardella, Mehdi Baradaran Tahoori, Gilles Gaudin
Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing. IEEE Trans. Multi Scale Comput. Syst. 2 (1) (2016)
Erya Deng, Lorena Anghel, Guillaume Prenat, Weisheng Zhao
Multi-context non-volatile content addressable memory using magnetic tunnel junctions. NANOARCH (2016)
Christophe Layer, Laurent Becker, Kotb Jabeur, Sylvain Claireux, Bernard Dieny, Guillaume Prenat, Gregory di Pendina, Stephane Gros, Pierre Paoli, Virgile Javerliac, Fabrice Bernard-Granger, Loïc Decloedt
Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories. ACM J. Emerg. Technol. Comput. Syst. 12 (4) (2016)
Erya Deng, You Wang, Zhaohao Wang, Jacques-Olivier Klein, Bernard Dieny, Guillaume Prenat, Weisheng Zhao
Robust magnetic full-adder with voltage sensing 2T/2MTJ cell. NANOARCH (2015)
Erya Deng, Yue Zhang, Wang Kang, Bernard Dieny, Jacques-Olivier Klein, Guillaume Prenat, Weisheng Zhao
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2015)
Guillaume Prenat, Gregory di Pendina, Christophe Layer, Olivier Goncalves, K. Jaber, Bernard Dieny, R. C. Sousa, Ioan Lucian Prejbeanu, Jean-Pierre Nozieres
Magnetic memories: From DRAM replacement to ultra low power logic chips. DATE (2014)
Gregory di Pendina, Guillaume Prenat, Bernard Dieny
InMRAM: Introductory course on Magnetic Random Access Memories for microelectronics students and engineers. EWME (2014)
Gregory di Pendina, Kotb Jabeur, Guillaume Prenat
Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures. ASP-DAC (2014)
Olivier Goncalves, Guillaume Prenat, Gregory di Pendina, Bernard Dieny
Non-volatile FPGAs based on spintronic devices. DAC (2013)
Weisheng Zhao, Guillaume Prenat, Jacques-Olivier Klein, Bernard Dieny, Claude Chappert, Dafine Ravelosona
Emerging hybrid logic circuits based on non-volatile magnetic memories. NEWCAS (2013)
Guillaume Prenat, Bernard Dieny, Jean-Pierre Nozieres, Gregory di Pendina, Kholdoun Torki
Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuits. ICCAD (2011)
Gregory di Pendina, Kholdoun Torki, Guillaume Prenat, Yoann Guillemenet, Lionel Torres
Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology. PATMOS (2011)
Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA. ACM Trans. Reconfigurable Technol. Syst. 2 (2) (2009)
Weisheng Zhao, Eric Belhaire, Bernard Dieny, Guillaume Prenat, Claude Chappert
TAS-MRAM based Non-volatile FPGA logic circuit. FPT (2007)
Guillaume Prenat, Mourad El Baraji, Wei Guo, Ricardo Sousa, Liliana Buda-Prejbeanu, Bernard Dieny, Virgile Javerliac, Jean-Pierre Nozieres, Weisheng Zhao, Eric Belhaire
CMOS/Magnetic Hybrid Architectures. ICECS (2007)
Guillaume Prenat, Salvador Mir, Diego Vázquez, Luís Rolíndez
A low-cost digital frequency testing approach for mixed-signal devices using SigmaDelta modulation. Microelectron. J. 36 (12) (2005)
Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir
testing circuit. ESSCIRC (2005)
Luís Rolíndez, Salvador Mir, Guillaume Prenat, Ahcène Bounceur
A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns. DATE (2004)