Lorena Anghel

ORCID

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 60

Top Venues

Grenoble Institute of Technology, France (PHD)

Education History

Grenoble Institute of Technology, France

PHD

Publications

Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. ETS (2024)
Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations. DATE (2024)
Soyed Tuhin Ahmed, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. CoRR (2024)
Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations. CoRR (2024)
Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI. CoRR (2024)
Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI. DATE (2024)
Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Spatial-SpinDrop: Spatial Dropout-based Binary Bayesian Neural Network with Spintronics Implementation. CoRR (2023)
Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Scale-Dropout: Estimating Uncertainty in Deep Neural Networks Using Stochastic Scale. CoRR (2023)
Manon Dampfhoffer, Thomas Mesquida, Emmanuel Hardy, Alexandre Valentian, Lorena Anghel
Leveraging Sparsity with Spiking Recurrent Neural Networks for Energy-Efficient Keyword Spotting. ICASSP (2023)
Ghislain Takam Tchendjou, Kamal Danouchi, Guillaume Prenat, Lorena Anghel
Spintronic Memristor-Based Binarized Ensemble Convolutional Neural Network Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (6) (2023)
Manon Dampfhoffer, Joel Minguet Lopez, Thomas Mesquida, Alexandre Valentian, Lorena Anghel
Improving the Robustness of Neural Networks to Noisy Multi-Level Non-Volatile Memory-based Synapses. IJCNN (2023)
Kamal Danouchi, Guillaume Prenat, Philippe Talatchian, Louis Hutin, Lorena Anghel
Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits. ISVLSI (2023)
Yunus Emre Aslan, Florian Cacho, T. Kumar, D. K. Janardan, A. Kumar, F. Giner, M. Faurichon, Lorena Anghel
Minimum SRAM Retention Voltage: Insight about optimizing Power Efficiency across Temperature Profile, Process Variation and Aging. IOLTS (2023)
Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation. DATE (2023)
Manon Dampfhoffer, Thomas Mesquida, Alexandre Valentian, Lorena Anghel
Are SNNs Really More Energy-Efficient Than ANNs? an In-Depth Hardware-Aware Study. IEEE Trans. Emerg. Top. Comput. Intell. 7 (3) (2023)
Lorena Anghel, Riccardo Cantoro, Riccardo Masante, Michele Portolan, Sandro Sartoni, Matteo Sonza Reorda
Self-Test Library Generation for In-Field Test of Path Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
SpinDrop: Dropout-Based Bayesian Binary Neural Networks With Spintronic Implementation. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (1) (2023)
Joao Henrique Quintino Palhares, Yann Beilliard, Jury Sandrini, Franck Arnaud, Kevin Garello, Guillaume Prenat, Lorena Anghel, Fabien Alibart, Dominique Drouin, Philippe Galy
A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses. CoRR (2023)
Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures. ACM Trans. Embed. Comput. Syst. 22 (5s) (2023)
Riccardo Cantoro, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan
Evaluating the Impact of Aging on Path-Delay Self-Test Libraries. DFT (2023)
Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, Gregory di Pendina, Patrick Girard, Arnaud Virazel
On Using Cell-Aware Methodology for SRAM Bit Cell Testing. ETS (2023)
Kamal Danouchi, Guillaume Prenat, Lorena Anghel
Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network. LATS (2022)
Manon Dampfhoffer, Thomas Mesquida, Alexandre Valentian, Lorena Anghel
Investigating Current-Based and Gating Approaches for Accurate and Energy-Efficient Spiking Recurrent Neural Networks. ICANN (3) (2022)
Stéphane Burel, Adrian Evans, Lorena Anghel
Improving DNN Fault Tolerance in Semantic Segmentation Applications. DFT (2022)
Etienne Becle, Guillaume Prenat, Philippe Talatchian, Lorena Anghel, Ioan Lucian Prejbeanu
A Fast, Energy Efficient and Tunable Magnetic Tunnel Junction Based Bitstream Generator for Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (8) (2022)
Nhat-Tan Phan, Lucile Soumah, Ahmed Sidi El Valli, Louis Hutin, Lorena Anghel, Ursula Ebels, Philippe Talatchian
Electrical Coupling of Perpendicular Superparamagnetic Tunnel Junctions for Probabilistic Computing. NANOARCH (2022)
Lorena Anghel, Florian Cacho
Design-Time Exploration for Process, Environment and Aging Compensation Techniques for Low Power Reliable-Aware Design. IEEE Trans. Emerg. Top. Comput. 10 (2) (2022)
Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices. NANOARCH (2022)
Etienne Becle, Philippe Talatchian, Guillaume Prenat, Lorena Anghel, Ioan Lucian Prejbeanu
Fast Behavioral VerilogA Compact Model for Stochastic MTJ. ESSDERC (2021)
Stéphane Burel, Adrian Evans, Lorena Anghel
Zero-Overhead Protection for CNN Weights. DFT (2021)
Florian Cacho, Lorena Anghel, Xavier Federspiel
Monitoring Setup and Hold Timing Limits. IRPS (2021)
Stéphane Burel, Adrian Evans, Lorena Anghel
MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN Accelerators. IOLTS (2021)
Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Elena I. Vatajelu
Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices. J. Electron. Test. 36 (3) (2020)
Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS (2020)
Riccardo Cantoro, Dario Foti, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan
New Perspectives on Core In-field Path Delay Test. ITC (2020)
Alberto Bosio, Ian O'Connor, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Elena I. Vatajelu, Giorgio Di Natale, Lorena Anghel, Surya Nagarajan, Moritz Fieback, Said Hamdioui
Rebooting Computing: The Challenges for Test and Reliability. DFT (2019)
Giorgio Di Natale, Elena Ioana Vatajelu, Kalpana Senthamarai Kannan, Lorena Anghel
Hidden-Delay-Fault Sensor for Test, Reliability and Security. DATE (2019)
Elena Ioana Vatajelu, Giorgio Di Natale, Lorena Anghel
Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN). VTS (2019)
Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Elena I. Vatajelu
Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model. LATS (2019)
Sergiu Mosanu, Xinfei Guo, Mohamed El-Hadedy, Lorena Anghel, Mircea Stan
Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints. FCCM (2019)
Ajith Sivadasan, Riddhi Jitendrakumar Shah, Vincent Huard, Florian Cacho, Lorena Anghel
NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOI. DATE (2018)
Lorena Anghel, Denys Ly, Giorgio Di Natale, Benoît Miramond, Elena Ioana Vatajelu, Elisa Vianello
Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies. VLSI-SoC (2018)
Muhammed Ceylan Morgül, Onur Tunali, Mustafa Altun, Luca Frontini, Valentina Ciriani, Elena Ioana Vatajelu, Lorena Anghel, Csaba Andras Moritz, Mircea R. Stan, Dan Alexandrescu
Integrated Synthesis Methodology for Crossbar Arrays. NANOARCH (2018)
Elena Ioana Vatajelu, Lorena Anghel, Jean-Michel Portal, Marc Bocquet, Guillaume Prenat
Resistive and Spintronic RAMs: Device, Simulation, and Applications. IOLTS (2018)
Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Marcello Traiola, Elena Ioana Vatajelu
Test and Reliability in Approximate Computing. J. Electron. Test. 34 (4) (2018)
Riddhi Jitendrakumar Shah, Florian Cacho, Vincent Huard, Souhir Mhira, D. Arora, P. Agarwal, S. Kumar, S. Balaraman, B. Singh, Lorena Anghel
Investigation of speed sensors accuracy for process and aging compensation. IRPS (2018)
Ajith Sivadasan, Armelle Notin, Vincent Huard, Etienne Maurin, Souhir Mhira, Florian Cacho, Lorena Anghel
Workload dependent reliability timing analysis flow. DATE (2017)
Florian Cacho, Ahmed Benhassain, Riddhi Jitendrakumar Shah, Souhir Mhira, Vincent Huard, Lorena Anghel
Investigation of critical path selection for in-situ monitors insertion. IOLTS (2017)
Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Baradaran Tahoori
Logic synthesis and testing techniques for switching nano-crossbar arrays. Microprocess. Microsystems 54 (2017)
Elena Ioana Vatajelu, Lorena Anghel
Reliability analysis of MTJ-based functional module for neuromorphic computing. IOLTS (2017)
Elena Ioana Vatajelu, Lorena Anghel
Fully-connected single-layer STT-MTJ-based spiking neural network under process variability. NANOARCH (2017)
Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Baradaran Tahoori
Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer. DSD (2016)
Florian Cacho, Ahmed Benhassain, Souhir Mhira, Ajith Sivadasan, Vincent Huard, P. Cathelin, V. Knopik, A. Jain, C. R. Parthasarathy, Lorena Anghel
Activity profiling: Review of different solutions to develop reliable and performant design. IOLTS (2016)
Erya Deng, Lorena Anghel, Guillaume Prenat, Weisheng Zhao
Multi-context non-volatile content addressable memory using magnetic tunnel junctions. NANOARCH (2016)
Ajith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel
Study of workload impact on BTI HCI induced aging of digital circuits. DATE (2016)
Niels Thole, Lorena Anghel, Görschwin Fey
A hybrid algorithm to conservatively check the robustness of circuits. ETS (2016)
Lorena Anghel, Ahmed Benhassain, Ajith Sivadasan, Florian Cacho, Vincent Huard
Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results. VTS (2016)
Ahmed Benhassain, Souhir Mhira, Florian Cacho, Vincent Huard, Lorena Anghel
In-situ slack monitors: taking up the challenge of on-die monitoring of variability and reliability. IVSW (2016)
Ajith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel
Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level Analysis. ERMAVSS@DATE (2016)
Ahmed Benhassain, Florian Cacho, Vincent Huard, Lorena Anghel
Early failure prediction by using in-situ monitors: Implementation and application results. ERMAVSS@DATE (2016)
Ahmed Benhassain, Florian Cacho, Vincent Huard, M. Saliva, Lorena Anghel, C. R. Parthasarathy, A. Jain, Fabien Giner
Timing in-situ monitors: Implementation strategy and applications results. CICC (2015)
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel
Application-independent testing of multilevel interconnect in mesh-based FPGAs. DTIS (2015)
M. Saliva, Florian Cacho, C. Ndiaye, Vincent Huard, D. Angot, Alain Bravaix, Lorena Anghel
Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology. IRPS (2015)
Marco Ottavi, Salvatore Pontarelli, Dimitris Gizopoulos, Cristiana Bolchini, Maria K. Michael, Lorena Anghel, Mehdi Baradaran Tahoori, Antonis M. Paschalis, Pedro Reviriego, Oliver Bringmann, Viacheslav Izosimov, Hans A. R. Manhaeve, Christos Strydis, Said Hamdioui
Dependable Multicore Architectures at Nanoscale: The View From Europe. IEEE Des. Test 32 (2) (2015)
M. Saliva, Florian Cacho, Vincent Huard, X. Federspiel, D. Angot, Ahmed Benhassain, Alain Bravaix, Lorena Anghel
Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI. DATE (2015)
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel
Cost-efficient of a cluster in a mesh SRAM-based FPGA. IOLTS (2014)
Lorena Anghel, Cristiana Bolchini, Salvatore Pontarelli
Editorial. Microprocess. Microsystems 38 (6) (2014)
Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. ISVLSI (2014)
Lorena Anghel, Mounir Benabdenbi, Frédéric Pétrot
System on chip project: Integration of a Motion-JPEG video decoder. EWME (2014)
Michael G. Dimopoulos, Yi Gang, Lorena Anghel, Mounir Benabdenbi, Nacer-Eddine Zergainoh, Michael Nicolaidis
Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip. Microprocess. Microsystems 38 (6) (2014)
Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. ICCD (2014)
Michael G. Dimopoulos, Yi Gang, Mounir Benabdenbi, Lorena Anghel, Nacer-Eddine Zergainoh, Michael Nicolaidis
Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip. IOLTS (2013)
T. Frank, Stéphane Moreau, Cédrick Chappaz, Patrick Leduc, Lucile Arnaud, Aurélie Thuaire, E. Chery, F. Lorut, Lorena Anghel, Gilles Poupon
Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric. Microelectron. Reliab. 53 (1) (2013)
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel
BIST for logic and local interconnect resources in a novel mesh of cluster FPGA. DFTS (2013)
Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky
Design for test and reliability in ultimate CMOS. DATE (2012)
Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis. J. Electron. Test. 28 (6) (2012)
Vladimir Pasca, Saif-Ur Rehman, Lorena Anghel, Mounir Benabdenbi
Efficient link-level error resilience in 3D NoCs. DDECS (2012)
Michael Nicolaidis, Vladimir Pasca, Lorena Anghel
Through-silicon-via built-in self-repair for aggressive 3D integration. IOLTS (2012)
Vladimir Pasca, Lorena Anghel, Michael Nicolaidis, Mounir Benabdenbi
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems. J. Electron. Test. 28 (1) (2012)
Aymen Fradi, Michael Nicolaidis, Lorena Anghel
Memory BIST with address programmability. IOLTS (2011)
Hai Yu, Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor. ETS (2011)
N. Ruiz Amador, Vincent Huard, E. Pion, Florian Cacho, Damien Croain, V. Robert, Sylvain Engels, Philippe Flatresse, Lorena Anghel
Bottom-up digital system-level reliability modeling. CICC (2011)
Claudia Rusu, Lorena Anghel, Dimiter Avresky
Adaptive inter-layer message routing in 3D networks-on-chip. Microprocess. Microsystems 35 (7) (2011)
Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi
Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis. LATW (2011)
Michael Nicolaidis, Vladimir Pasca, Lorena Anghel
I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems. ETS (2011)
Claudia Rusu, Lorena Anghel, Dimiter Avresky
RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip. IOLTS (2010)
Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi
Fault tolerant communication in 3D integrated systems. DSN Workshops (2010)
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi
Configurable serial fault-tolerant link for communication in 3D integrated systems. IOLTS (2010)
Michael Nicolaidis, Vladimir Pasca, Lorena Anghel
Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems. IOLTS (2010)
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Riccardo Locatelli, Massimo Coppola
Error resilience of intra-die and inter-die communication with 3D spidergon STNoC. DATE (2010)
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi
Configurable fault-tolerant link for inter-die communication in 3D on-chip networks. ETS (2010)
Hai Yu, Michael Nicolaidis, Lorena Anghel
An effective approach to detect logic soft errors in digital circuits based on GRAAL. ISQED (2009)
Lorena Anghel
HOT TOPIC - Concurrent SoC development and end-to-end planning. DATE (2009)
Claudia Rusu, Cristian Grecu, Lorena Anghel
Communication Aware Recovery Configurations for Networks-on-Chip. IOLTS (2008)
Claudia Rusu, Cristian Grecu, Lorena Anghel
Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems. DELTA (2008)
Claudia Rusu, Cristian Grecu, Lorena Anghel
Improving the scalability of checkpoint recovery for networks-on-chip. ISCAS (2008)
Christophe Le Blanc, Éric Colinet, Jérôme Juillard, Lorena Anghel
Digital Implementation of a BIST Method based on Binary Observations. DSD (2008)
Claudia Rusu, Antonin Bougerol, Lorena Anghel, Cécile Weulersse, Nadine Buard, S. Benhammadi, Nicolas Renaud, Guillaume Hubert, Frederic Wrobel, Thierry Carrière, Rémi Gaillard
Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells. IOLTS (2007)
Cristiano Lazzari, Cristiano Santos, Adriel Ziesemer, Lorena Anghel, Ricardo Reis
Efficient timing closure with a transistor level design flow. VLSI-SoC (2007)
Lorena Anghel, Michael Nicolaidis
Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies. IWANN (2007)

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Publication Activity (10 Years)

Top Topics

Top Venues

Lorena Anghel