Zied Marrakchi

Publication Activity (10 Years)

Years Active: 2005-2022
Publications (10 Years): 22

Top Venues

ARC

HPCS

IDT

Int. J. Reconfigurable Comput.

Pierre and Marie Curie University, Paris, France (PHD)

Education History

Pierre and Marie Curie University, Paris, France

PHD

Publications

Hajer Saidi, Mariem Turki, Zied Marrakchi, Mohamed Abid, Abdulfattah Obeid
Development and Analysis of Novel Mesh of Tree-based embedded FPGA. J. Supercomput. 78 (16) (2022)
Khouloud Bouaziz, Sonda Chtourou, Zied Marrakchi, Abdulfattah Mohammad Obeid, Mohamed Abid
Mesh of Trees FPGA Architecture: Exploration and Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (9) (2022)
Hajer Saidi, Mariem Turki, Zied Marrakchi, Hela Ben Ahmed, Abdulfattah Obeid, Mohamed Abid
Exploration of Word Width and Cluster Size Effects on Tree-Based Embedded FPGA Using an Automation Framework. J. Circuits Syst. Comput. 30 (13) (2021)
Hajer Saidi, Mariem Turki, Zied Marrakchi, Abdulfattah Obeid, Mohamed Abid
Implementation of Reed Solomon Encoder on Low-Latency Embedded FPGA in Flexible SoC based on ARM Processor. IWCMC (2020)
Hajer Saidi, Mariem Turki, Zied Marrakchi, Abdulfattah Obeid, Mohamed Abid
Novel Synthesizable eFPGA based on Island Network with Multilevel Switch Boxes. AICCSA (2020)
Khouloud Bouaziz, Sonda Chtourou, Zied Marrakchi, Abdulfattah Mohammad Obeid, Mohamed Abid
A-Part: Top-Down Clustering Approach for Mesh of Clusters FPGA. ISDA (2020)
Khouloud Bouaziz, Sonda Chtourou, Zied Marrakchi, Mohamed Abid, Abdulfattah Obeid
Exploration of Clustering Algorithms effects on Mesh of Clusters based FPGA Architecture Performance. HPCS (2019)
Hajer Saidi, Mariem Turki, Zied Marrakchi, M. S. Ben Saleh, Mohamed Abid
New CAD Tools to ConFigure Tree-Based Embedded FPGA. HPCS (2019)
Khouloud Bouaziz, Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Abdulfattah Mohammad Obeid
Impact of Clustering Algorithms on the performance of Multilevel Switch Boxes FPGA with Long Wires. IWCMC (2019)
Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez
Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support. Turkish J. Electr. Eng. Comput. Sci. 25 (2017)
Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez
On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA. HPCS (2017)
Khouloud Bouaziz, Sonda Chtourou, Zied Marrakchi, Abdulfattah Mohammad Obeid, Mohamed Abid
Rebuilding synthesized design hierarchy based on instances path names of flattened netlist. IDT (2016)
Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Habib Mehrez, Mohamed Abid
Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance. PDP (2016)
Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez
Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization. IDT (2016)
Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez
The effect of interconnect depopulation on FPGA performances in terms of power, area and delay. HPCS (2016)
Zied Marrakchi, Eman El Mandouh
Tutorial 2: "Challenges of FPGA-based prototyping & debugging". IDT (2016)
Hajer Saidi, Mariem Turki, Zied Marrakchi, Mohammed S. BenSaleh, Mohamed Abid
Embedded FPGA accelerator for Wireless Sensor Network nodes. IDT (2016)
Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez
Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires. Microprocess. Microsystems 40 (2016)
Vinod Pangracious, Zied Marrakchi, Habib Mehrez
Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA. IEEE Micro 35 (6) (2015)
Sonda Chtourou, Zied Marrakchi, Vinod Pangracious, Emna Amouri, Habib Mehrez, Mohamed Abid
Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization. ARC (2015)
Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid
Signal multiplexing approach to improve inter-FPGA bandwidth of prototyping platform. Des. Autom. Embed. Syst. 19 (3) (2015)
Nidhameddine Belhadj, Nejmeddine Bahri, Zied Marrakchi, Mohamed Ali Ben Ayed, Nouri Masmoudi, Habib Mehrez
H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture. IET Comput. Digit. Tech. 9 (5) (2015)
Vinod Pangracious, Zied Marrakchi, Nizar Beltaief, Habib Mehrez, Umer Farooq
Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA. DTIS (2014)
Abdulfattah Mohammad Obeid, Syed Manzoor Qasim, Mohammed S. BenSaleh, Zied Marrakchi, Habib Mehrez, Heni Ghariani, Mohamed Abid
Flexible reconfigurable architecture for DSP applications. SoCC (2014)
Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Habib Mehrez
Power consumption analysis for mesh based FPGA. DTIS (2014)
Nidhameddine Belhadj, Zied Marrakchi, Mohamed Ali Ben Ayed, Nouri Masmoudi, Habib Mehrez
MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder. Int. J. Embed. Real Time Commun. Syst. 5 (2) (2014)
Nidhameddine Belhadj, Mohamed Ali Ben Ayed, Nouri Masmoudi, Zied Marrakchi, Habib Mehrez
MPSoC architecture for Component Level Parallelism of H.264/AVC intra prediction encoding chain on SoCLib platform. ATSIP (2014)
Sonda Chtourou, Mohamed Abid, Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez
Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation. 3DIC (2014)
Alp Kiliç, Zied Marrakchi, Habib Mehrez
A Top-Down Optimization Methodology for Mutually Exclusive Applications. Int. J. Reconfigurable Comput. 2014 (2014)
Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. ISVLSI (2014)
Vinod Pangracious, Mohamed Sahbi Marrakchi, Habib Mehrez, Zied Marrakchi
On wiring delays reduction of tree-based FPGA using 3-D fabric. SoCC (2014)
Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez
Architecture level optimization of 3-dimensional tree-based FPGA. Microelectron. J. 45 (4) (2014)
Karim M. Abdellatif, Roselyne Chotin-Avot, Zied Marrakchi, Habib Mehrez, Qingshan Tang
Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only). FPGA (2014)
Qingshan Tang, Matthieu Tuna, Zied Marrakchi, Habib Mehrez
Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist. ARC (2013)
Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid
Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform. Int. J. Reconfigurable Comput. 2013 (2013)
Vinod Pangracious, Zied Marrakchi, Habib Mehrez
Design and optimization of heterogeneous tree-based FPGA using 3D technology. FPT (2013)
Vinod Pangracious, Habib Mehrez, Zied Marrakchi
TSV count minimization and thermal analysis for 3D Tree-based FPGA. ICICDT (2013)
Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA. Microelectron. J. 44 (12) (2013)
Mariem Turki, Habib Mehrez, Zied Marrakchi, Mohamed Abid
Partitioning constraints and signal routing approach for multi-FPGA prototyping platform. ISSoC (2013)
Arwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner, Mounir Benabdenbi, Roselyne Chotin-Avot, Emna Amouri, Habib Mehrez, Zied Marrakchi
A defect-tolerant cluster in a mesh SRAM-based FPGA. FPT (2013)
Vinod Pangracious, Habib Mehrez, Umer Farooq, Zied Marrakchi
High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA). FPGAworld (2013)
Emna Amouri, Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Zied Marrakchi
Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture. ReConFig (2013)
Vinod Pangracious, Habib Mehrez, Zied Marrakchi
Architecture level TSV count minimization methodology for 3D tree-based FPGA. COOL Chips (2013)
Emna Amouri, Habib Mehrez, Zied Marrakchi
Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA. Int. J. Reconfigurable Comput. 2013 (2013)
Vinod Pangracious, Habib Mehrez, Zied Marrakchi
Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis. NEWCAS (2013)
Vinod Pangracious, Emna Amouri, Habib Mehrez, Zied Marrakchi
Physical design exploration of 3D tree-based FPGA architecture. ACM Great Lakes Symposium on VLSI (2013)
Vinod Pangracious, Habib Mehrez, Zied Marrakchi
Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology. 3DIC (2013)
Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez
Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA. ARC (2013)
Nidhameddine Belhadj, Nejmeddine Bahri, Mohamed Ali Ben Ayed, Zied Marrakchi, Habib Mehrez
Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC. SSD (2013)
Mariem Turki, Zied Marrakchi, Mohamed Abid
New synthesis approach of hierarchical benchmarks for hardware prototyping. DTIS (2013)
Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid
Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform. ARC (2013)
Vinod Pangracious, Habib Mehrez, Nizar Beltaief, Zied Marrakchi, Umer Farooq
Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA). ReConFig (2013)
Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi
A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA. Microprocess. Microsystems 36 (8) (2012)
Mariem Turki, Habib Mehrez, Zied Marrakchi
Multi-FPGA prototyping environment: Large benchmark generation and signals routing. ReConFig (2012)
Alp Kiliç, Zied Marrakchi, Matthieu Tuna, Habib Mehrez
A logic sharing synthesis tool for mutually exclusive applications. DTIS (2012)
Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi
Exploration of Heterogeneous FPGA Architectures. Int. J. Reconfigurable Comput. 2011 (2011)
Emna Amouri, Zied Marrakchi, Habib Mehrez
Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA. ReCoSoC (2011)
Husain Parvez, Zied Marrakchi, Alp Kiliç, Habib Mehrez
Application-Specific FPGA using heterogeneous logic blocks. ACM Trans. Reconfigurable Technol. Syst. 4 (3) (2011)
Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez
Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. ARC (2011)
Husain Parvez, Zied Marrakchi, Habib Mehrez
Application Specific FPGA Using Heterogeneous Logic Blocks. ARC (2010)
Mariem Turki, Mohamed Abid, Zied Marrakchi, Habib Mehrez
Routability driven placement for mesh-based FPGA architecture. IDT (2010)
Husain Parvez, Zied Marrakchi, Habib Mehrez
Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). FPGA (2010)
Emna Amouri, Zied Marrakchi, Habib Mehrez
Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA. APCCAS (2010)
Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez
Exploration of Heterogeneous FPGA Architectures. ReCoSoC (2010)
Zied Marrakchi, Husain Parvez, Alp Kiliç, Habib Mehrez, Hmaied Marrakchi
On the optimization of FPGA area depending on target applications. APCCAS (2010)
Zied Marrakchi, Hayder Mrabet, Umer Farooq, Habib Mehrez
FPGA Interconnect Topologies Exploration. Int. J. Reconfigurable Comput. 2009 (2009)
Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ReConFig (2009)
Husain Parvez, Zied Marrakchi, Habib Mehrez
ASIF: Application Specific Inflexible FPGA. FPT (2009)
Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez
Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. ICECS (2009)
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez
Efficient tree topology for FPGA interconnect network. ACM Great Lakes Symposium on VLSI (2008)
Husain Parvez, Zied Marrakchi, Umer Farooq, Habib Mehrez
A new coarse-grained FPGA architecture exploration environment. FPT (2008)
Husain Parvez, Zied Marrakchi, Habib Mehrez
Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. ReConFig (2008)
Umer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez
The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. ReConFig (2008)
Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez
Efficient Mesh of Tree Interconnect for FPGA Architecture. FPT (2007)
Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. NOCS (2007)
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot
Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. ReCoSoC (2006)
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez
A multilevel hierarchical interconnection structure for FPGA. FPGA (2006)
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. ICCAD (2006)
Zied Marrakchi, Hayder Mrabet, Habib Mehrez
A new Multilevel Hierarchical MFPGA and its suitable configuration tools. ISVLSI (2006)
Zied Marrakchi, Hayder Mrabet, Habib Mehrez
Configuration tools for a new multilevel hierarchical FPGA. FPGA (2006)
Zied Marrakchi, Hayder Mrabet, Habib Mehrez
Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. ReConFig (2005)
Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot
Implementation of Scalable Embedded FPGA for SOC. ReCoSoC (2005)

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Publication Activity (10 Years)

Top Topics

Top Venues

Zied Marrakchi