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Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture.
Emna Amouri
Adrien Blanchardon
Roselyne Chotin-Avot
Habib Mehrez
Zied Marrakchi
Published in:
ReConFig (2013)
Keyphrases
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high speed
hardware implementation
real time
hardware design
dedicated hardware
low cost
hardware architecture
signal processing
d mesh
delaunay triangulation
software implementation
fpga implementation
systolic array
xilinx virtex
arbitrary topology
computationally efficient
three dimensional