Habib Mehrez

ORCID

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 20

Top Venues

ReConFig

ARC

Microprocess. Microsystems

Int. J. Reconfigurable Comput.

Publications

Umer Farooq, Imran Baig, Muhammad Khurram Bhatti, Habib Mehrez, Arun Kumar, Manoj Gupta
Prototyping using multi-FPGA platform: A novel and complete flow. Microprocess. Microsystems 96 (2023)
Umer Farooq, Habib Mehrez
Pre-Silicon Verification Using Multi-FPGA Platforms: A Review. J. Electron. Test. 37 (1) (2021)
Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Maminionja Ravoson, Habib Mehrez
Novel architectural space exploration environment for multi-FPGA based prototyping systems. Microprocess. Microsystems 56 (2018)
Umer Farooq, Habib Mehrez, Muhammad Khurram Bhatti
Inter-FPGA interconnect topologies exploration for multi-FPGA systems. Des. Autom. Embed. Syst. 22 (1-2) (2018)
Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez
Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support. Turkish J. Electr. Eng. Comput. Sci. 25 (2017)
Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez
AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations. J. Signal Process. Syst. 88 (1) (2017)
Umer Farooq, Habib Mehrez, Muhammad Khurram Bhatti
Comparison of direct and switch-based inter-FPGA routing interconnect for multi-FPGA systems. ReConFig (2017)
Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez
On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA. HPCS (2017)
Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez
AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAs. CS2@HiPEAC (2016)
Muhammad Moazam Azeem, Roselyne Chotin-Avot, Umer Farooq, Maminionja Ravoson, Habib Mehrez
Multiple FPGAs based prototyping and debugging with complete design flow. IDT (2016)
Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Habib Mehrez, Mohamed Abid
Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance. PDP (2016)
Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez
Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization. IDT (2016)
Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez
The effect of interconnect depopulation on FPGA performances in terms of power, area and delay. HPCS (2016)
Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Maminionja Ravoson, Mariem Turki, Habib Mehrez
Inter-FPGA routing environment for performance exploration of multi-FPGA systems. RSP (2016)
Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Zouha Cherif, Maminionja Ravoson, Saqib Khan, Habib Mehrez
Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration. DSD (2016)
Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez
Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires. Microprocess. Microsystems 40 (2016)
Vinod Pangracious, Zied Marrakchi, Habib Mehrez
Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA. IEEE Micro 35 (6) (2015)
Sonda Chtourou, Zied Marrakchi, Vinod Pangracious, Emna Amouri, Habib Mehrez, Mohamed Abid
Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization. ARC (2015)
Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid
Signal multiplexing approach to improve inter-FPGA bandwidth of prototyping platform. Des. Autom. Embed. Syst. 19 (3) (2015)
Nidhameddine Belhadj, Nejmeddine Bahri, Zied Marrakchi, Mohamed Ali Ben Ayed, Nouri Masmoudi, Habib Mehrez
H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture. IET Comput. Digit. Tech. 9 (5) (2015)
Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez
FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm. ARC (2014)
Alp Kiliç, Delaram Haghighitalab, Habib Mehrez, Hassan Aboushady
Low-power comb decimation filter for RF Sigma-Delta ADCs. ISCAS (2014)
Vinod Pangracious, Zied Marrakchi, Nizar Beltaief, Habib Mehrez, Umer Farooq
Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA. DTIS (2014)
Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri
Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA. ReConFig (2014)
Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. FPL (2014)
Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez
Low cost solutions for secure remote reconfiguration of FPGAs. Int. J. Embed. Syst. 6 (2/3) (2014)
Abdulfattah Mohammad Obeid, Syed Manzoor Qasim, Mohammed S. BenSaleh, Zied Marrakchi, Habib Mehrez, Heni Ghariani, Mohamed Abid
Flexible reconfigurable architecture for DSP applications. SoCC (2014)
Qingshan Tang, Habib Mehrez, Matthieu Tuna
Multi-FPGA prototyping board issue: the FPGA I/O bottleneck. ICSAMOS (2014)
Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Habib Mehrez
Power consumption analysis for mesh based FPGA. DTIS (2014)
Qingshan Tang, Matthieu Tuna, Habib Mehrez
Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only). FPGA (2014)
Nidhameddine Belhadj, Zied Marrakchi, Mohamed Ali Ben Ayed, Nouri Masmoudi, Habib Mehrez
MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder. Int. J. Embed. Real Time Commun. Syst. 5 (2) (2014)
Nidhameddine Belhadj, Mohamed Ali Ben Ayed, Nouri Masmoudi, Zied Marrakchi, Habib Mehrez
MPSoC architecture for Component Level Parallelism of H.264/AVC intra prediction encoding chain on SoCLib platform. ATSIP (2014)
Jung Kyu Chae, Paul Mougeat, Jean-Arnaud Francois, Roselyne Chotin-Avot, Habib Mehrez
A reference-based specification tool for creating reliable library development specifications. NEWCAS (2014)
Qingshan Tang, Matthieu Tuna, Habib Mehrez
Performance Comparison between Multi-FPGA Prototyping Platforms: Hardwired Off-the-Shelf, Cabling, and Custom. FCCM (2014)
Boukary Ouattara, Lise Doyen, David Ney, Habib Mehrez, Pirouz Bazargan-Sabet
Power grid redundant path contribution in system on chip (SoC) robustness against electromigration. Microelectron. Reliab. 54 (9-10) (2014)
Sonda Chtourou, Mohamed Abid, Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez
Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation. 3DIC (2014)
Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez
Authenticated encryption on FPGAs from the static part to the reconfigurable part. Microprocess. Microsystems 38 (6) (2014)
Alp Kiliç, Zied Marrakchi, Habib Mehrez
A Top-Down Optimization Methodology for Mutually Exclusive Applications. Int. J. Reconfigurable Comput. 2014 (2014)
Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. ISVLSI (2014)
Vinod Pangracious, Mohamed Sahbi Marrakchi, Habib Mehrez, Zied Marrakchi
On wiring delays reduction of tree-based FPGA using 3-D fabric. SoCC (2014)
Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez
Architecture level optimization of 3-dimensional tree-based FPGA. Microelectron. J. 45 (4) (2014)
Karim M. Abdellatif, Roselyne Chotin-Avot, Zied Marrakchi, Habib Mehrez, Qingshan Tang
Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only). FPGA (2014)
Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri
Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy. FPL (2014)
Qingshan Tang, Matthieu Tuna, Habib Mehrez
Routing algorithm for multi-FPGA based systems using multi-point physical tracks. RSP (2013)
Qingshan Tang, Matthieu Tuna, Zied Marrakchi, Habib Mehrez
Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist. ARC (2013)
Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid
Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform. Int. J. Reconfigurable Comput. 2013 (2013)
Vinod Pangracious, Zied Marrakchi, Habib Mehrez
Design and optimization of heterogeneous tree-based FPGA using 3D technology. FPT (2013)
Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez
Efficient AES-GCM for VPNs using FPGAs. MWSCAS (2013)
Vinod Pangracious, Habib Mehrez, Zied Marrakchi
TSV count minimization and thermal analysis for 3D Tree-based FPGA. ICICDT (2013)
Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA. Microelectron. J. 44 (12) (2013)
Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez
High speed authenticated encryption for slow changing key applications using reconfigurable devices. Wireless Days (2013)
Mariem Turki, Habib Mehrez, Zied Marrakchi, Mohamed Abid
Partitioning constraints and signal routing approach for multi-FPGA prototyping platform. ISSoC (2013)
Arwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner, Mounir Benabdenbi, Roselyne Chotin-Avot, Emna Amouri, Habib Mehrez, Zied Marrakchi
A defect-tolerant cluster in a mesh SRAM-based FPGA. FPT (2013)
Vinod Pangracious, Habib Mehrez, Umer Farooq, Zied Marrakchi
High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA). FPGAworld (2013)
Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez
Protecting FPGA bitstreams using authenticated encryption. NEWCAS (2013)
Jung Kyu Chae, Severine Bertrand, Pierre-Francois Ollagnon, Paul Mougeat, Jean-Arnaud Francois, Roselyne Chotin-Avot, Habib Mehrez
Efficient state-dependent power model for multi-bit flip-flop banks. MWSCAS (2013)
Emna Amouri, Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Zied Marrakchi
Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture. ReConFig (2013)
Vinod Pangracious, Habib Mehrez, Zied Marrakchi
Architecture level TSV count minimization methodology for 3D tree-based FPGA. COOL Chips (2013)
Emna Amouri, Habib Mehrez, Zied Marrakchi
Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA. Int. J. Reconfigurable Comput. 2013 (2013)
Sophie Belloeil-Dupuis, Roselyne Chotin-Avot, Habib Mehrez
Exploring redundant arithmetics in computer-aided design of arithmetic datapaths. Integr. 46 (2) (2013)
Vinod Pangracious, Habib Mehrez, Zied Marrakchi
Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis. NEWCAS (2013)
Vinod Pangracious, Emna Amouri, Habib Mehrez, Zied Marrakchi
Physical design exploration of 3D tree-based FPGA architecture. ACM Great Lakes Symposium on VLSI (2013)
Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez
Improved method for parallel AES-GCM cores using FPGAs. ReConFig (2013)
Arwa Ben Dhia, Samuel N. Pagliarini, Lirida Alves de Barros Naviner, Habib Mehrez, Philippe Matherat
A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs. Microelectron. Reliab. 53 (9-11) (2013)
Vinod Pangracious, Habib Mehrez, Zied Marrakchi
Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology. 3DIC (2013)
Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez
Lightweight and compact solutions for secure reconfiguration of FPGAs. ReConFig (2013)
Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez
Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA. ARC (2013)
Nidhameddine Belhadj, Nejmeddine Bahri, Mohamed Ali Ben Ayed, Zied Marrakchi, Habib Mehrez
Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC. SSD (2013)
Jung Kyu Chae, Paul Mougeat, Jean-Arnaud Francois, Roselyne Chotin-Avot, Habib Mehrez
A formalism of the specifications for library development. SoCC (2013)
Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid
Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform. ARC (2013)
Vinod Pangracious, Habib Mehrez, Nizar Beltaief, Zied Marrakchi, Umer Farooq
Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA). ReConFig (2013)
Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez
Efficient parallel-pipelined GHASH for message authentication. ReConFig (2012)
Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi
A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA. Microprocess. Microsystems 36 (8) (2012)
Mariem Turki, Habib Mehrez, Zied Marrakchi
Multi-FPGA prototyping environment: Large benchmark generation and signals routing. ReConFig (2012)
Qingshan Tang, Habib Mehrez, Matthieu Tuna
Design for prototyping of a parameterizable cluster-based Multi-Core System-on-Chip on a multi-FPGA board. RSP (2012)
Alp Kiliç, Zied Marrakchi, Matthieu Tuna, Habib Mehrez
A logic sharing synthesis tool for mutually exclusive applications. DTIS (2012)
Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi
Exploration of Heterogeneous FPGA Architectures. Int. J. Reconfigurable Comput. 2011 (2011)
Sophie Belloeil-Dupuis, Roselyne Chotin-Avot, Habib Mehrez
Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools. ISQED (2011)
Emna Amouri, Zied Marrakchi, Habib Mehrez
Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA. ReCoSoC (2011)
Husain Parvez, Zied Marrakchi, Alp Kiliç, Habib Mehrez
Application-Specific FPGA using heterogeneous logic blocks. ACM Trans. Reconfigurable Technol. Syst. 4 (3) (2011)
Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez
Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. ARC (2011)
Husain Parvez, Zied Marrakchi, Habib Mehrez
Application Specific FPGA Using Heterogeneous Logic Blocks. ARC (2010)
Mariem Turki, Mohamed Abid, Zied Marrakchi, Habib Mehrez
Routability driven placement for mesh-based FPGA architecture. IDT (2010)
Husain Parvez, Zied Marrakchi, Habib Mehrez
Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). FPGA (2010)
Ludovic Noury, Habib Mehrez
A flexible realtime system for broadband time-frequency analysis in 130 NM CMOS. ICECS (2010)
Emna Amouri, Zied Marrakchi, Habib Mehrez
Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA. APCCAS (2010)
Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez
Exploration of Heterogeneous FPGA Architectures. ReCoSoC (2010)
Zied Marrakchi, Husain Parvez, Alp Kiliç, Habib Mehrez, Hmaied Marrakchi
On the optimization of FPGA area depending on target applications. APCCAS (2010)
Zied Marrakchi, Hayder Mrabet, Umer Farooq, Habib Mehrez
FPGA Interconnect Topologies Exploration. Int. J. Reconfigurable Comput. 2009 (2009)
Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ReConFig (2009)
Husain Parvez, Zied Marrakchi, Habib Mehrez
ASIF: Application Specific Inflexible FPGA. FPT (2009)
Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez
Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. ICECS (2009)
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez
Efficient tree topology for FPGA interconnect network. ACM Great Lakes Symposium on VLSI (2008)
Ana Abril, Habib Mehrez, Frédéric Pétrot, Jean Gobert, Carolina Miro
Estimation et optimisation de la consommation dans les SoC utilisant la simulation précise au cycle. Tech. Sci. Informatiques 27 (1-2) (2008)
Husain Parvez, Zied Marrakchi, Umer Farooq, Habib Mehrez
A new coarse-grained FPGA architecture exploration environment. FPT (2008)
Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez
Arithmetic Data Path Optimization Using Borrow-Save Representation. ISVLSI (2008)
Husain Parvez, Zied Marrakchi, Habib Mehrez
Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. ReConFig (2008)
Umer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez
The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. ReConFig (2008)
Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez
Efficient Mesh of Tree Interconnect for FPGA Architecture. FPT (2007)
Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. NOCS (2007)

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Publication Activity (10 Years)

Top Topics

Top Venues

Habib Mehrez