Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology.
Vinod PangraciousHabib MehrezZied MarrakchiPublished in: 3DIC (2013)
Keyphrases
- high speed
- low cost
- single chip
- case study
- global optimization
- optimization method
- gate array
- key technologies
- rapid development
- signal processing
- optimization problems
- general purpose
- cost effective
- neural network
- real time
- data processing
- low power
- hardware implementation
- web services
- constrained optimization
- field programmable gate array
- digital signal processors