Mounir Benabdenbi

Publication Activity (10 Years)

Years Active: 2000-2021
Publications (10 Years): 5

Top Topics

Skeleton Extraction

Variable Precision

Top Venues

J. Electron. Test.

Publications

Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory
FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method. ISVLSI (2021)
Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory
FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach. DTIS (2020)
Ali Skaf, Mona Ezzadeen, Mounir Benabdenbi, Laurent Fesquet
On-Line Adjustable Precision Computing. DTIS (2019)
Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Marcello Traiola, Elena Ioana Vatajelu
Test and Reliability in Approximate Computing. J. Electron. Test. 34 (4) (2018)
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel
Application-independent testing of multilevel interconnect in mesh-based FPGAs. DTIS (2015)
Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux
On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel
Cost-efficient of a cluster in a mesh SRAM-based FPGA. IOLTS (2014)
Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. ISVLSI (2014)
Lorena Anghel, Mounir Benabdenbi, Frédéric Pétrot
System on chip project: Integration of a Motion-JPEG video decoder. EWME (2014)
Michael G. Dimopoulos, Yi Gang, Lorena Anghel, Mounir Benabdenbi, Nacer-Eddine Zergainoh, Michael Nicolaidis
Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip. Microprocess. Microsystems 38 (6) (2014)
Michael G. Dimopoulos, Yi Gang, Mounir Benabdenbi, Lorena Anghel, Nacer-Eddine Zergainoh, Michael Nicolaidis
Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip. IOLTS (2013)
Arwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner, Mounir Benabdenbi, Roselyne Chotin-Avot, Emna Amouri, Habib Mehrez, Zied Marrakchi
A defect-tolerant cluster in a mesh SRAM-based FPGA. FPT (2013)
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel
BIST for logic and local interconnect resources in a novel mesh of cluster FPGA. DFTS (2013)
Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis. J. Electron. Test. 28 (6) (2012)
Vladimir Pasca, Saif-Ur Rehman, Lorena Anghel, Mounir Benabdenbi
Efficient link-level error resilience in 3D NoCs. DDECS (2012)
Vladimir Pasca, Lorena Anghel, Michael Nicolaidis, Mounir Benabdenbi
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems. J. Electron. Test. 28 (1) (2012)
Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux
Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure. VTS (2011)
Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi
Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis. LATW (2011)
Zhen Zhang, Alain Greiner, Mounir Benabdenbi
Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components. IOLTS (2010)
Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi
Fault tolerant communication in 3D integrated systems. DSN Workshops (2010)
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi
Configurable serial fault-tolerant link for communication in 3D integrated systems. IOLTS (2010)
Etienne Faure, Gabriel Marchesan Almeida, Mounir Benabdenbi, Pascal Benoit, Fabien Clermidy, François Pêcheux, Gilles Sassatelli, Lionel Torres
SoCs. DASIP (2010)
Etienne Faure, Mounir Benabdenbi, François Pêcheux
Distributed online software monitoring of manycore architectures. IOLTS (2010)
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi
Configurable fault-tolerant link for inter-die communication in 3D on-chip networks. ETS (2010)
Mounir Benabdenbi, François Pêcheux, Etienne Faure
On-line test and monitoring of multi-processor SoCs: A software-based approach. LATW (2009)
Matthieu Tuna, Mounir Benabdenbi, Alain Greiner
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester. VTS (2007)
Alain Greiner, Frédéric Pétrot, M. Carrier, Mounir Benabdenbi, Roselyne Chotin-Avot, Raphaël Labayrade
MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation. ReCoSoC (2006)
Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna
STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores. DATE (2004)
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing. J. Electron. Test. 18 (4-5) (2002)
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
Testing TAPed cores and wrapped cores with the same test access mechanism. DATE (2001)
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip. DATE (2000)
Walid Maroufi, Mounir Benabdenbi, Meryem Marzouki
Solving the I/O Bandwidth Problem in System on a Chip Testing. SBCCI (2000)