Katell Morin-Allory

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 20

Top Venues

VLSI-SoC

ISVLSI

ICECS

VLSI-SoC (Selected Papers)

University of Rennes 1, France (PHD)

Education History

University of Rennes 1, France

PHD

Publications

Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory
Formal Resilience Metric Characterization in Complex Digital Systems. ETS (2024)
Cristiano Merio, Xavier Lesage, Ali Naimi, Sylvain Engels, Katell Morin-Allory, Laurent Fesquet
Method for Data-Driven Pruning in Micropipeline Circuits. VLSI-SoC (2023)
Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory
Formal Temporal Characterization of Register Vulnerability in Digital Circuits. ISVLSI (2023)
Diana Kalel, Jean-Christophe Brignone, Laurent Fesquet, Katell Morin-Allory
A Generic CDC Modeling for Data Stability Verification. ICECS (2023)
Yoan Decoudu, Katell Morin-Allory, Laurent Fesquet
A High-Level Design Flow for Locally Body Biased Asynchronous Circuits. VLSI-SoC (2021)
Julie Roux, Katell Morin-Allory, Vincent Beroulle, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier
Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism. VLSI-SoC (2021)
Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory
FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method. ISVLSI (2021)
Julie Roux, Katell Morin-Allory, Vincent Beroulle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier, Régis Leveugle
FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level Models. VLSI-SoC (Selected Papers) (2021)
Julie Roux, Vincent Beroulle, Katell Morin-Allory, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier
High Level Fault Injection Method for Evaluating Critical System Parameter Ranges. ICECS (2020)
Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory
FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach. DTIS (2020)
Julie Roux, Vincent Beroulle, Katell Morin-Allory, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier
Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems. DDECS (2020)
Yoan Decoudu, Jean Simatic, Katell Morin-Allory, Laurent Fesquet
From High-Level Synthesis to Bundled-Data Circuits. SAMOS (2020)
Laurent Fesquet, Yoan Decoudu, Alexis Rodrigo Iga Jadue, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Rodrigo Possamai Bastos, Katell Morin-Allory, Sylvain Engels
A Distributed Body-Biasing Strategy for Asynchronous Circuits. VLSI-SoC (2019)
Yoan Decoudu, Jean Simatic, Pauline Alexandre, Katell Morin-Allory, Laurent Fesquet
Comparison of Synchronous and Asynchronous FIR Filter Architectures. EBCCSP (2019)
Guillaume Plassan, Katell Morin-Allory, Dominique Borrione
Mining Missing Assumptions from Counter-Examples. ACM Trans. Embed. Comput. Syst. 18 (1) (2019)
Fatemeh Negin Javaheri, Katell Morin-Allory, Dominique Borrione
Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (5) (2017)
Guillaume Plassan, Katell Morin-Allory, Dominique Borrione
Extraction of missing formal assumptions in under-constrained designs. MEMOCODE (2017)
Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Shaker Sarwary, Dominique Borrione
Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings. VLSI-SoC (Selected Papers) (2016)
Mejid Kebaili, Jean-Christophe Brignone, Katell Morin-Allory
Clock domain crossing formal verification: a meta-model. HLDVT (2016)
Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Fahim Rahim, Shaker Sarwary, Dominique Borrione
Conclusively verifying clock-domain crossings in very large hardware designs. VLSI-SoC (2016)
Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione
Efficient and Correct by Construction Assertion-Based Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 23 (12) (2015)
Mejid Kebaili, Katell Morin-Allory, Jean-Christophe Brignone, Dominique Borrione
Enabler-based synchronizer model for clock domain crossing static verification. FDL (2015)
Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione
SyntHorus-2: Automatic prototyping from PSL. VLSI-SoC (2013)
Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione
Fast prototyping from assertions: A pragmatic approach. MEMOCODE (2013)
Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet, Alejandro Chagoya
Does asynchronous technology bring robustness in synchronous circuit monitoring? FDL (2011)
Chao Yan, Florent Ouchet, Laurent Fesquet, Katell Morin-Allory
Formal Verification of C-element Circuits. ASYNC (2011)
Florent Ouchet, Katell Morin-Allory, Laurent Fesquet
C-elements for Hardened Self-timed Circuits. PATMOS (2011)
Florent Ouchet, Katell Morin-Allory, Laurent Fesquet
Delay Insensitivity Does Not Mean Slope Insensitivity! ASYNC (2010)
Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet
Synthesis of asynchronous monitors for critical electronic systems. DDECS (2010)
Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic
Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (9) (2010)
Yann Oddos, Katell Morin-Allory, Dominique Borrione
From Assertion-Based Verification to Assertion-Based Synthesis. VLSI-SoC (2009)
Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic
MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI (2009)
Khaled Alsayeg, Katell Morin-Allory, Laurent Fesquet
RAT-based formal verification of QDI asynchronous controllers. FDL (2009)
Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre
High-level symbolic simulation for automatic model extraction. DDECS (2009)
Yann Oddos, Katell Morin-Allory, Dominique Borrione
Assertion-Based Design with Horus. MEMOCODE (2008)
Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic
Proving and disproving assertion rewrite rules with automated theorem provers. HLDVT (2008)
Katell Morin-Allory, Eric Gascard, Dominique Borrione
Synthesis of Property Monitors for Online Fault Detection. J. Circuits Syst. Comput. 16 (6) (2007)
Yann Oddos, Katell Morin-Allory, Dominique Borrione
Prototyping Generators for On-line Test Vector Generation Based on PSL Properties. DDECS (2007)
Katell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione
Asynchronous online-monitoring of logical and temporal assertions. FDL (2007)
Katell Morin-Allory, Dominique Borrione
On-line Monitoring of Properties Built on Regular Expressions. FDL (2006)
Katell Morin-Allory, Laurent Fesquet, Dominique Borrione
Asynchronous Assertion Monitors for multi-Clock Domain System Verification. IEEE International Workshop on Rapid System Prototyping (2006)
Yann Oddos, Katell Morin-Allory, Dominique Borrione
On-Line Test Vector Generation from Temporal Constraints Written in PSL. VLSI-SoC (2006)
Katell Morin-Allory, Dominique Borrione
Proven correct monitors from PSL specifications. DATE (2006)
Katell Morin-Allory, David Cachera
Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic. CHARME (2005)
Katell Morin-Allory, Dominique Borrione
A proof of correctness for the construction of property monitors. HLDVT (2005)
David Cachera, Katell Morin-Allory
Verification of safety properties for parameterized regular systems. ACM Trans. Embed. Comput. Syst. 4 (2) (2005)
David Cachera, Katell Morin-Allory
Verification of Control Properties in the Polyhedral Model. MEMOCODE (2003)

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Publication Activity (10 Years)

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Katell Morin-Allory