Régis Leveugle

ORCID

Publication Activity (10 Years)

Years Active: 1989-2024
Publications (10 Years): 33

Top Venues

Publications

Sami El Amraoui, Régis Leveugle, Paolo Maistri
Choose your Path: Control of Ring Oscillators EMFI Susceptibility through FPGA P&R Constraints. DDECS (2024)
Régis Leveugle, Nathan Hocquette, Charles Labarre, Romain Plumaugat, Loic Tcharoukian, Valentin Martinoli, Yannick Teglia
Secured Bus as a Countermeasure against Covert Channels: NEORV32 Case Study. LATS (2024)
Sami El Amraoui, Aghiles Douadi, Régis Leveugle, Paolo Maistri
Harmonic Response of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection. LATS (2024)
Luc Noizette, Florent Miller, Thierry Colladant, Youri Helen, Régis Leveugle
Using Application Profiling based on a Virtual Platform for SoC Fault Tolerance Assessment. PRIME (2022)
Valentin Martinoli, Yannick Teglia, Abdellah Bouagoun, Régis Leveugle
Recovering Information on the CVA6 RISC-V CPU with a Baremetal Micro-Architectural Covert Channel. IOLTS (2022)
Valentin Martinoli, Yannick Teglia, Abdellah Bouagoun, Régis Leveugle
CVA6's Data cache: Structure and Behavior. CoRR (2022)
Julie Roux, Katell Morin-Allory, Vincent Beroulle, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier
Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism. VLSI-SoC (2021)
Julie Roux, Katell Morin-Allory, Vincent Beroulle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier, Régis Leveugle
FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level Models. VLSI-SoC (Selected Papers) (2021)
Paolo Maistri, Vincent Reynaud, Michele Portolan, Régis Leveugle
Secure Test with RSNs: Seamless Authenticated Extended Confidentiality. NEWCAS (2021)
Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle, Giorgio Di Natale
Security EDA Extension through P1687.1 and 1687 Callbacks. ITC (2021)
Julie Roux, Vincent Beroulle, Katell Morin-Allory, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier
High Level Fault Injection Method for Evaluating Critical System Parameter Ranges. ICECS (2020)
Julie Roux, Vincent Beroulle, Katell Morin-Allory, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier
Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems. DDECS (2020)
Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS (2020)
Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle
Dynamic Authentication-Based Secure Access to Test Infrastructure. ETS (2020)
Alessandro Savino, Michele Portolan, Régis Leveugle, Stefano Di Carlo
Approximate computing design exploration through data lifetime metrics. ETS (2019)
Michele Portolan, Alessandro Savino, Régis Leveugle, Stefano Di Carlo, Alberto Bosio, Giorgio Di Natale
Alternatives to Fault Injections for Early Safety/Security Evaluations. ETS (2019)
Marc Merandat, Vincent Reynaud, Emanuele Valea, Jérôme Quévremont, Nicolas Valette, Paolo Maistri, Régis Leveugle, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre, Giorgio Di Natale
A Comprehensive Approach to a Trusted Test Infrastructure. IVSW (2019)
Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan De Castro, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model. FDTC (2018)
Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. IOLTS (2018)
Régis Leveugle, Asma Mkhinini, Paolo Maistri
Hardware Support for Security in the Internet of Things: From Lightweight Countermeasures to Accelerated Homomorphic Encryption. Inf. 9 (5) (2018)
Asma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki
HLS design of a hardware accelerator for Homomorphic Encryption. DDECS (2017)
Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Régis Leveugle
Reliability of computing systems: From flip flops to variables. IOLTS (2017)
Régis Leveugle
Tutorial 1: "New approaches towards early dependability evaluation of digital integrated systems". IDT (2016)
Lydie Terras, Yannick Teglia, Michel Agoyan, Régis Leveugle
Taking into account indirect jumps or calls in continuous control-flow checking. IDT (2016)
Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle
Analysis of laser-induced errors: RTL fault models versus layout locality characteristics. Microprocess. Microsystems 47 (2016)
K. Chibani, Michele Portolan, Régis Leveugle
Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations. IOLTS (2016)
Simon Pontie, Paolo Maistri, Régis Leveugle
Dummy operations in scalar multiplication over elliptic curves: A tradeoff between security and performance. Microprocess. Microsystems 47 (2016)
Simon Pontie, Alban Bourge, Adrien Prost-Boucle, Paolo Maistri, Olivier Muller, Régis Leveugle, Frédéric Rousseau
HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic. DSD (2016)
Charalampos Ananiadis, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle
On the development of a new countermeasure based on a laser attack RTL fault model. DATE (2016)
Asma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki, Mohsen Machhout
A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption. IDT (2016)
Régis Leveugle, A. Chahed, Paolo Maistri, Athanasios Papadimitriou, David Hély, Vincent Beroulle
On fault injections for early security evaluation vs. laser-based attacks. IVSW (2016)
Athanasios Papadimitriou, Marios Tampas, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle
Validation of RTL laser fault injection model with respect to layout information. HOST (2015)
C. Jayet-Griffon, M.-A. Cornelie, Paolo Maistri, Philippe Elbaz-Vincent, Régis Leveugle
Polynomial multipliers for fully homomorphic encryption on FPGA. ReConFig (2015)
K. Chibani, Mohamed Ben Jrad, Michele Portolan, Régis Leveugle
Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor. VLSI-SoC (2014)
K. Chibani, Salma Bergaoui, Michele Portolan, Régis Leveugle
Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options. ICECS (2014)
Salma Bergaoui, Pierre Vanhauwaert, Régis Leveugle
IDSM: An improved disjoint signature monitoring scheme for processor behavioral checking. LATW (2014)
Paolo Maistri, Régis Leveugle, Lilian Bossuet, Alain Aubert, Viktor Fischer, Bruno Robisson, Nicolas Moro, Philippe Maurine, Jean-Max Dutertre, Mathieu Lisart
Electromagnetic analysis and fault injection onto secure circuits. VLSI-SoC (2014)
Simon Pontie, Paolo Maistri, Régis Leveugle
An Elliptic Curve Crypto-Processor Secured by Randomized Windows. DSD (2014)
Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Guillaume Hubert, Stephan De Castro, Jean-Max Dutertre, Alexandre Sarafianos, Noemie Boher, Mathieu Lisart, Joel Damiens, Philippe Candelier, Clément Tavernier
Laser-induced fault effects in security-dedicated circuits. VLSI-SoC (2014)
Pierre Vanhauwaert, Paolo Maistri, Régis Leveugle, Athanasios Papadimitriou, David Hély, Vincent Beroulle
On error models for RTL security evaluations. DTIS (2014)
Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, Marie-Lise Flottes, David Hély, Guillaume Hubert, Régis Leveugle, Feng Lu, Paolo Maistri, Athanasios Papadimitriou, Bruno Rouzeyre, Clément Tavernier, Pierre Vanhauwaert
Laser-Induced Fault Effects in Security-Dedicated Circuits. VLSI-SoC (Selected Papers) (2014)
Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks. DATE (2014)
Diego Alberto, Paolo Maistri, Régis Leveugle
Electromagnetic attacks on embedded devices: A model of probe-circuit power coupling. DTIS (2014)
Diego Alberto, Paolo Maistri, Régis Leveugle
Forecasting the Effects of Electromagnetic Fault Injections on Embedded Cryptosystems. Inf. Secur. J. A Glob. Perspect. 22 (5-6) (2013)
Mohamed Ben Jrad, Régis Leveugle
Automated design flow for no-cost configuration error detection in sram-based FPGAs. ReConFig (2013)
Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle
An evaluation of an AES implementation protected against EM analysis. ACM Great Lakes Symposium on VLSI (2013)
Mohamed Ben Jrad, Régis Leveugle
Evaluating a low cost robustness improvement in SRAM-based FPGAs. IOLTS (2013)
Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle
Countermeasures against EM analysis for a secured FPGA-based AES implementation. ReConFig (2013)
Salma Bergaoui, A. Wecxsteen, Régis Leveugle
Detailed Analysis of Compilation Options for Robust Software-based Embedded Systems. J. Electron. Test. 29 (2) (2013)
A. Wecxsteen, Salma Bergaoui, Régis Leveugle
Detailed analysis of compilation options for robust software-based embedded systems. LATW (2012)
Mohamed Ben Jrad, Régis Leveugle
Pattern-based injections in processors implemented on SRAM-based FPGAs. LATW (2012)
Paolo Maistri, Régis Leveugle
10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard. DSD (2011)
Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. J. Cryptol. 24 (2) (2011)
Renaud Clavel, Laurence Pierre, Régis Leveugle
Towards Robustness Analysis Using PVS. ITP (2011)
Salma Bergaoui, Régis Leveugle
Impact of Software Optimization on Variable Lifetimes in a Microprocessor-Based System. DELTA (2011)
Régis Leveugle, Mohamed Ben Jrad
A new methodology for accurate predictive robustness analysis of designs implemented in SRAM-based FPGAs. ICECS (2010)
Régis Leveugle
Early Robustness Evaluation of Digital Integrated Systems. FDL (2010)
Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. ASAP (2010)
Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin
Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. ETS (2010)
Régis Leveugle, A. Calvez, Paolo Maistri, Pierre Vanhauwaert
Statistical fault injection: Quantified error and confidence. DATE (2009)
Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud
Complementary Formal Approaches for Dependability Analysis. DFT (2009)
Paolo Maistri, Régis Leveugle
Towards automated fault pruning with Petri Nets. IOLTS (2009)
Gaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin
Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. VTS (2009)
Régis Leveugle
Chip level security: Why ? How ? ICECS (2008)
Paolo Maistri, Cyril Excoffon, Régis Leveugle
Software BIST capabilities of a symmetric cipher. ICECS (2008)
Gaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle
Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. IOLTS (2008)
Paolo Maistri, Cyril Excoffon, Régis Leveugle
Software Self-Testing of a Symmetric Cipher with Error Detection Capability. IOLTS (2008)
Pierre Vanhauwaert, Michele Portolan, Régis Leveugle, Philippe Roche
Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system. ICECS (2008)
Paolo Maistri, Régis Leveugle
Double-Data-Rate Computation as a Countermeasure against Fault Analysis. IEEE Trans. Computers 57 (11) (2008)
Régis Leveugle
Dependability issues in SRAM-based FPGA design. ICECS (2007)
V. Maingot, Jean Baptiste Ferron, Régis Leveugle, Vincent Pouget, Alexandre Douin
Configuration errors analysis in SRAM-based FPGAs: Software tool and practical results. Microelectron. Reliab. 47 (9-11) (2007)
Yannick Monnet, Marc Renaudin, Régis Leveugle
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. IOLTS (2007)
Michele Portolan, Régis Leveugle
Effective Checkpoint and Rollback Using Hardware/OS Collaboration. DFT (2007)
Ian O'Connor, Junchen Liu, Frédéric Gaffiot, Fabien Prégaldiny, Christophe Lallement, Cristell Maneux, Johnny Goguet, Sébastien Fregonese, Thomas Zimmer, Lorena Anghel, Trong-Trinh Dang, Régis Leveugle
CNTFET Modeling and Reconfigurable Logic-Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2007)
Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle
Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections. DFT (2007)
Régis Leveugle, Abdelaziz Ammari, V. Maingot, E. Teyssou, Pascal Moitrel, Christophe Mourtel, Nathalie Feyt, Jean-Baptiste Rigaud, Assia Tria
Experimental evaluation of protections against laser-induced faults and consequences on fault modeling. DATE (2007)
Régis Leveugle
Early Analysis of Fault-based Attack Effects in Secure Circuits. IEEE Trans. Computers 56 (10) (2007)
Christophe Smekens, Régis Leveugle
On Deratings to Refine System-Level Failure Rate Estimations. ICECS (2007)
Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle
A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection. FDTC (2007)
Pierre Vanhauwaert, Régis Leveugle, Philippe Roche
Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis. VLSI-SoC (2006)
Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel
Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. FDTC (2006)
Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet
Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. IOLTS (2006)
Yannick Monnet, Marc Renaudin, Régis Leveugle
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. IEEE Trans. Computers 55 (9) (2006)
Abdelaziz Ammari, Régis Leveugle, Bogdan Nicolescu, Yvon Savaria
Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection. DELTA (2006)
Pierre Vanhauwaert, Régis Leveugle, Philippe Roche
A Flexible SoPC-based Fault Injection Environment. DDECS (2006)
Vincent Maingot, Régis Leveugle
Error Detection Code Efficiency for Secure Chips. ICECS (2006)
Régis Leveugle, V. Maingot
On the Use of Information Redundancy When Designing Secure Chips. DDECS (2006)
Yannick Monnet, Marc Renaudin, Régis Leveugle
Hardening Techniques against Transient Faults for Asynchronous Circuits. IOLTS (2005)
Michele Portolan, Régis Leveugle
On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. IOLTS (2005)
Régis Leveugle
A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations. IOLTS (2005)
Régis Leveugle
Introduction to the Special Session on Secure Implementations. IOLTS (2005)
Abdelaziz Ammari, K. Hadjiat, Régis Leveugle
Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation. J. Electron. Test. 21 (4) (2005)
Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert
Evaluation of SET and SEU Effects at Multiple Abstraction Levels. IOLTS (2005)
Yannick Monnet, Marc Renaudin, Régis Leveugle
Asynchronous circuits transient faults sensitivity evaluation. DAC (2005)
Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert
On-Line Testing for Secure Implementations: Design and Validation. IOLTS (2005)
Michele Portolan, Régis Leveugle
Towards a Secure and Reliable System. EUC (2005)
Abdelaziz Ammari, K. Hadjiat, Régis Leveugle
On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation. IOLTS (2004)
Yannick Monnet, Marc Renaudin, Régis Leveugle
Asynchronous Circuits Sensitivity to Fault Injection. IOLTS (2004)
Régis Leveugle, D. Cimonnet, Abdelaziz Ammari
System-Level Dependability Analysis with RT-Level Fault Injection Accuracy. DFT (2004)
Régis Leveugle, Abdelaziz Ammari
Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow. DATE (2004)

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Publication Activity (10 Years)

Top Topics

Top Venues

Régis Leveugle