Sophie Dupuis

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 27

Top Topics

Intellectual Property

Ultra Low Power

Top Venues

Publications

Sophie Dupuis, Nassim Riadi, Clémy Moroukian, Florence Azaïs, Marie-Lise Flottes
Logic Locking: Exploration of a new key-gate based on tristate logic. LATS (2024)
Nassim Riadi, Florent Bruguier, Pascal Benoit, Sophie Dupuis, Marie-Lise Flottes
Power Analysis Attack Against post-SAT Logic Locking schemes. ETS (2024)
F. Almeida, Levent Aksoy, Q.-L. Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini
Resynthesis-based Attacks Against Logic Locking. CoRR (2023)
Honorio Martín, Sophie Dupuis, Giorgio Di Natale, Luis Entrena
Using Approximate Circuits Against Hardware Trojans. IEEE Des. Test 40 (3) (2023)
Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
Hybrid Protection of Digital FIR Filters. IEEE Trans. Very Large Scale Integr. Syst. 31 (6) (2023)
Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
Hybrid Protection of Digital FIR Filters. CoRR (2023)
Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini
Resynthesis-based Attacks Against Logic Locking. ISQED (2023)
Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
High-level Intellectual Property Obfuscation via Decoy Constants. CoRR (2021)
Quang-Linh Nguyen, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
On Preventing SAT Attack with Decoy Key-Inputs. ISVLSI (2021)
Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
High-level Intellectual Property Obfuscation via Decoy Constants. IOLTS (2021)
Quang-Linh Nguyen, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
A Secure Scan Controller for Protecting Logic Locking. IOLTS (2020)
Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssade, Arnaud Virazel
Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. IOLTS (2020)
Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
SECCS: SECure Context Saving for IoT Devices. CoRR (2019)
Marc Merandat, Vincent Reynaud, Emanuele Valea, Jérôme Quévremont, Nicolas Valette, Paolo Maistri, Régis Leveugle, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre, Giorgio Di Natale
A Comprehensive Approach to a Trusted Test Infrastructure. IVSW (2019)
Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Sophie Dupuis, Bruno Rouzeyre
Providing Confidentiality and Integrity in Ultra Low Power IoT Devices. DTIS (2019)
Sophie Dupuis, Marie-Lise Flottes
Logic Locking: A Survey of Proposed Methods and Evaluation Metrics. J. Electron. Test. 35 (3) (2019)
Honorio Martín, Luis Entrena, Sophie Dupuis, Giorgio Di Natale
A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation. IOLTS (2018)
Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre
A New Secure Stream Cipher for Scan Chain Encryption. IVSW (2018)
Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre
Encryption of test data: which cipher is better? PRIME (2018)
Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
SI ECCS: SECure context saving for IoT devices. DTIS (2018)
Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead. IEEE Des. Test 35 (2) (2018)
Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
Hacking the Control Flow error detection mechanism. IVSW (2017)
Papa-Sidi Ba, Sophie Dupuis, Palanichamy Manikandan, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique. ISVLSI (2016)
Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
Using outliers to detect stealthy hardware trojan triggering? IVSW (2016)
Marie-Lise Flottes, Sophie Dupuis, Papa-Sidi Ba, Bruno Rouzeyre
On the limitations of logic testing for detecting Hardware Trojans Horses. DTIS (2015)
Papa-Sidi Ba, Palanichamy Manikandan, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
Hardware Trojan prevention using layout-level design approach. ECCTD (2015)
Sophie Dupuis, Papa-Sidi Ba, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
New testing procedure for finding insertion sites of stealthy hardware trojans. DATE (2015)
Sophie Dupuis, Papa-Sidi Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans. IOLTS (2014)
Sophie Dupuis, Ludovic Noury, Nicolas Fel
A regular fabric design methodology for applications requiring specific layout-level design rules. Microelectron. J. 45 (2) (2014)
Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis. Inf. Secur. J. A Glob. Perspect. 22 (5-6) (2013)
Amitabh Das, Jean DaRolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
Secure JTAG Implementation Using Schnorr Protocol. J. Electron. Test. 29 (2) (2013)
Ludovic Noury, Sophie Dupuis, Nicolas Fel
A reference low-complexity structured ASIC. ISCAS (2012)