Patrick Girard

ORCID

Publication Activity (10 Years)

Years Active: 1992-2024
Publications (10 Years): 104

Top Venues

Publications

Aibin Yan, Yu Chen, Zhongyu Gao, Tianming Ni, Zhengfeng Huang, Jie Cui, Patrick Girard, Xiaoqing Wen
FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell. IEEE Trans. Circuits Syst. II Express Briefs 71 (4) (2024)
Aibin Yan, Zhixing Li, Zhongyu Gao, Jing Zhang, Zhengfeng Huang, Tianming Ni, Jie Cui, Xiaolei Wang, Patrick Girard, Xiaoqing Wen
MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (7) (2024)
Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel
A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. DATE (2024)
Aibin Yan, Litao Wang, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS. IEEE Trans. Very Large Scale Integr. Syst. 32 (1) (2024)
Aibin Yan, Zhuoyuan Lin, Guangzhu Liu, Qingyang Zhang, Zhengfeng Huang, Jie Cui, Xiaoqing Wen, Patrick Girard
Nonvolatile and SEU-Recoverable Latch Based on FeFET and CMOS for Energy-Harvesting Devices. ISCAS (2024)
Aibin Yan, Chen Dong, Xing Guo, Jie Song, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen
IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications. ACM Great Lakes Symposium on VLSI (2024)
Xhesila Xhafa, Patrick Girard, Arnaud Virazel
Learning-Based Characterization Models for Quality Assurance of Emerging Memory Technologies. ETS (2023)
Aibin Yan, Zhen Zhou, Liang Ding, Jie Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard
High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology. DATE (2023)
Aibin Yan, Jing Xiang, Zhengfeng Huang, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing Wen
Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications. ITC-Asia (2023)
Aibin Yan, Shaojie Wei, Zhixing Li, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
Design of Low-Cost Approximate CMOS Full Adders. ISCAS (2023)
Aibin Yan, Fan Xia, Tianming Ni, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
A Low Overhead and Double-Node-Upset Self-Recoverable Latch. ITC-Asia (2023)
Aibin Yan, Shaojie Wei, Jinjun Zhang, Jie Cui, Jie Song, Tianming Ni, Patrick Girard, Xiaoqing Wen
A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications. ACM Great Lakes Symposium on VLSI (2023)
Aibin Yan, Yuting He, Xiaoxiao Niu, Jie Cui, Tianming Ni, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications. IEEE Des. Test 40 (4) (2023)
Aibin Yan, Chao Zhou, Shaojie Wei, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness. ITC-Asia (2023)
Aibin Yan, Aoran Cao, Zhengfeng Huang, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen, Jiliang Zhang
Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications. IEEE Trans. Emerg. Top. Comput. 11 (4) (2023)
Aibin Yan, Jing Xiang, Yang Chang, Zhengfeng Huang, Jie Cui, Patrick Girard, Xiaoqing Wen
Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications. Microelectron. J. 139 (2023)
L. Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel
Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture. ETS (2023)
Aibin Yan, Zhixing Li, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen
Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments. IEEE Trans. Aerosp. Electron. Syst. 59 (3) (2023)
Aibin Yan, Runqi Liu, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen, Jiliang Zhang
Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs 70 (6) (2023)
Aibin Yan, Zhixing Li, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen
LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (6) (2023)
Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, Gregory di Pendina, Patrick Girard, Arnaud Virazel
On Using Cell-Aware Methodology for SRAM Bit Cell Testing. ETS (2023)
Aibin Yan, Liang Ding, Zhen Zhou, Zhengfeng Huang, Jie Cui, Patrick Girard, Xiaoqing Wen
A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage. ATS (2022)
Aibin Yan, Yu Chen, Shukai Song, Zijie Zhai, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications. ACM Great Lakes Symposium on VLSI (2022)
Aibin Yan, Zhen Zhou, Shaojie Wei, Jie Cui, Yong Zhou, Tianming Ni, Patrick Girard, Xiaoqing Wen
A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology. ACM Great Lakes Symposium on VLSI (2022)
Aibin Yan, Kuikui Qian, Jie Cui, Ningning Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard
A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications. VTS (2022)
Aibin Yan, Zhixing Li, Shiwei Huang, Zijie Zhai, Xiangyu Cheng, Jie Cui, Tianming Ni, Xiaoqing Wen, Patrick Girard
SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments. DATE (2022)
Aibin Yan, Shukai Song, Jixiang Zhang, Jie Cui, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen, Patrick Girard
Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS. ITC-Asia (2022)
Aibin Yan, Zhelong Xu, Xiangfeng Feng, Jie Cui, Zhili Chen, Tianming Ni, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments. IEEE Trans. Emerg. Top. Comput. 10 (1) (2022)
Riccardo Cantoro, Francesco Garau, Patrick Girard, Nima Kolahimahmoudi, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel
Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries. ETS (2022)
Aibin Yan, Zhengzheng Fan, Liang Ding, Jie Cui, Zhengfeng Huang, Qijun Wang, Hao Zheng, Patrick Girard, Xiaoqing Wen
Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications. IEEE Trans. Aerosp. Electron. Syst. 58 (1) (2022)
Kangwei Xu, Dongrong Zhang, Qiang Ren, Yuanqing Cheng, Patrick Girard
All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits. ACM J. Emerg. Technol. Comput. Syst. 18 (4) (2022)
J. Lefevre, P. Debaud, Patrick Girard, Arnaud Virazel
A Generic Fast and Low Cost BIST Solution for CMOS Image Sensors. ETS (2022)
Aibin Yan, Zhihui He, Jing Xiang, Jie Cui, Yong Zhou, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications. ACM Great Lakes Symposium on VLSI (2022)
Jinbo Chen, Chengcheng Lu, Jiacheng Ni, Xiaochen Guo, Patrick Girard, Yuanqing Cheng
DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect. IEEE Trans. Very Large Scale Integr. Syst. 29 (7) (2021)
Aibin Yan, Zhihui He, Jun Zhou, Jie Cui, Tianming Ni, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard
Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications. Microelectron. J. 111 (2021)
Neha Gupta, Nikhil Agrawal, Narendra Singh Dhakad, Ambika Prasad Shah, Santosh Kumar Vishvakarma, Patrick Girard
Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits. ACM Great Lakes Symposium on VLSI (2021)
Aibin Yan, Aoran Cao, Zhelong Xu, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications. J. Electron. Test. 37 (4) (2021)
S. Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar
Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference. ISQED (2021)
Syed Farah Naz, Ambika Prasad Shah, Suhaib Ahmed, Patrick Girard, Michael Waltl
Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum dot Cellular Automata. ETS (2021)
J. Lefevre, Philippe Debaud, Patrick Girard, Arnaud Virazel
A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors. ITC (2021)
Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard
Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing. IOLTS (2021)
Riccardo Cantoro, Patrick Girard, Riccardo Masante, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel
Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement. IOLTS (2021)
Pablo Ilha Vaz, Patrick Girard, Arnaud Virazel, Hassen Aziza
Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors. IEEE Trans. Very Large Scale Integr. Syst. 29 (6) (2021)
P. d'Hondt, Aymen Ladhar, Patrick Girard, Arnaud Virazel
A Learning-Based Methodology for Accelerating Cell-Aware Model Generation. DATE (2021)
Aibin Yan, Aoran Cao, Zhengzheng Fan, Zhelong Xu, Tianming Ni, Patrick Girard, Xiaoqing Wen
A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments. ACM Great Lakes Symposium on VLSI (2021)
Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels
. ETS (2021)
Patrick Girard, Yuanqing Cheng, Arnaud Virazel, Wei Zhao, Rajendra Bishnoi, Mehdi B. Tahoori
A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. Proc. IEEE 109 (2) (2021)
L. Ammoura, Marie-Lise Flottes, Patrick Girard, Arnaud Virazel
Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures. DTIS (2021)
Aibin Yan, Zhelong Xu, Kang Yang, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications. IEEE Trans. Aerosp. Electron. Syst. 56 (4) (2020)
S. Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, A. Ladhar
A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns. ITC (2020)
Aibin Yan, Xiangfeng Feng, Xiaohu Zhao, Hang Zhou, Jie Cui, Zuobin Ying, Patrick Girard, Xiaoqing Wen
HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications. DAC (2020)
Aibin Yan, Yan Chen, Jun Zhou, Jie Cui, Tianming Ni, Xiaoqing Wen, Patrick Girard
A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets. ATS (2020)
Jinbo Chen, Keren Liu, Xiaochen Guo, Patrick Girard, Yuanqing Cheng
DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache. ISQED (2020)
Panagiota Papavramidou, Michael Nicolaidis, Patrick Girard
An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAM. IOLTS (2020)
Aibin Yan, Yafei Ling, Jie Cui, Zhili Chen, Zhengfeng Huang, Jie Song, Patrick Girard, Xiaoqing Wen
Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2020)
Ambika Prasad Shah, Patrick Girard
Impact of Aging on Soft Error Susceptibility in CMOS Circuits. IOLTS (2020)
Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard
QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction. ETS (2020)
Aibin Yan, Zhelong Xu, Jie Cui, Zuobin Ying, Zhengfeng Huang, Huaguo Liang, Patrick Girard, Xiaoqing Wen
Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications. ISCAS (2020)
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
Maximizing Yield for Approximate Integrated Circuits. DATE (2020)
Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel
Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS (2020)
Zhengda Dou, Aibin Yan, Jun Zhou, Yuanjie Hu, Yan Chen, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing Wen
Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors. ITC-Asia (2020)
Bastien Deveautour, Arnaud Virazel, Patrick Girard, Valentin Gherman
On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits. J. Electron. Test. 36 (1) (2020)
Aibin Yan, Yuanjie Hu, Jie Cui, Zhili Chen, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen
Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment. IEEE Trans. Computers 69 (6) (2020)
Pablo Ilha Vaz, Patrick Girard, Arnaud Virazel, Hassen Aziza
A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace Applications. IOLTS (2020)
Aibin Yan, Yan Chen, Yuanjie Hu, Jun Zhou, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing Wen
Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets. IEEE Trans. Circuits Syst. (12) (2020)
S. Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, A. Ladhar
Learning-Based Cell-Aware Defect Diagnosis of Customer Returns. ETS (2020)
Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssade, Arnaud Virazel
Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. IOLTS (2020)
Aibin Yan, Yan Chen, Zhelong Xu, Zhili Chen, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications. IEEE Trans. Aerosp. Electron. Syst. 56 (5) (2020)
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
A Survey of Testing Techniques for Approximate Integrated Circuits. Proc. IEEE 108 (12) (2020)
Safa Mhamdi, Arnaud Virazel, Patrick Girard, Alberto Bosio, Etienne Auvray, Eric Faehn, Aymen Ladhar
Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip. IOLTS (2019)
Hassen Aziza, Mathieu Moreau, Annie Pérez, Arnaud Virazel, Patrick Girard
A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks. NEWCAS (2019)
Aibin Yan, Zhen Wu, Jun Zhou, Yuanjie Hu, Yan Chen, Zuobin Ying, Xiaoqing Wen, Patrick Girard
Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications. ATS (2019)
Aibin Yan, Zhen Wu, Lu Lu, Zhili Chen, Jie Song, Zuobin Ying, Patrick Girard, Xiaoqing Wen
Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications. ATS (2019)
Aibin Yan, Jun Zhou, Yuanjie Hu, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets. IEEE Access 7 (2019)
Patrick Girard
Power-aware testing in the Era of IoT. ISQED (2018)
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
Testing approximate digital circuits: Challenges and opportunities. LATS (2018)
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits. DFT (2018)
Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, Etienne Auvray
Scan-Chain Intra-Cell Aware Testing. IEEE Trans. Emerg. Top. Comput. 6 (2) (2018)
Patrick Girard
Industrial Experiences in Low Power Electronics. J. Low Power Electron. 14 (3) (2018)
Patrick Girard
A Special Section On Machine Learning and Artificial Intelligence In Low Power Electronics. J. Low Power Electron. 14 (4) (2018)
Patrick Girard
Low Power Electronics: A Compilation of Emerging Ideas and Efficient Solutions. J. Low Power Electron. 14 (2) (2018)
Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman
Is aproximate computing suitable for selective hardening of arithmetic circuits? DTIS (2018)
Tien-Phu Ho, Eric Faehn, Arnaud Virazel, Alberto Bosio, Patrick Girard
An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs. ITC (2018)
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits. DDECS (2018)
Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
Towards approximation during test of Integrated Circuits. DDECS (2017)
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
Towards digital circuit approximation by exploiting fault simulation. EWDTS (2017)
G. Harcha, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi
An effective fault-injection framework for memory reliability enhancement perspectives. DTIS (2017)
Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
Microprocessor Testing: Functional Meets Structural Test. J. Circuits Syst. Comput. 26 (8) (2017)
Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality. J. Low Power Electron. 13 (1) (2017)
Patrick Girard
New and Future Trends in Low Power Electronics. J. Low Power Electron. 13 (3) (2017)
Alberto Bosio, Arnaud Virazel, Patrick Girard, Mario Barbareschi
Approximate computing: Design & test for integrated circuits. LATS (2017)
Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. J. Electron. Test. 33 (1) (2017)
Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. J. Circuits Syst. Comput. 26 (8) (2017)
Alberto Bosio, Philippe Debaud, Patrick Girard, Stephane Guilhot, Miroslav Valka, Arnaud Virazel
Auto-adaptive ultra-low power IC. DTIS (2016)
Alberto Bosio, Patrick Girard, Arnaud Virazel
Test of low power circuits: Issues and industrial practices. ICECS (2016)
Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo Bonet Zordan
An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED (2016)
Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. ISVLSI (2016)
Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
An effective approach for functional test programs compaction. DDECS (2016)
Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
A Hybrid Power Estimation Technique to improve IP power models quality. VLSI-SoC (2016)
Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
A low-cost susceptibility analysis methodology to selectively harden logic circuits. ETS (2016)

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Publication Activity (10 Years)

Top Topics

Top Venues

Patrick Girard