Luigi Dilillo

ORCID

Publication Activity (10 Years)

Years Active: 2003-2023
Publications (10 Years): 30

Top Venues

Publications

Annachiara Ruospo, Ernesto Sánchez, Lucas Matana Luza, Luigi Dilillo, Marcello Traiola, Alberto Bosio
A Survey on Deep Learning Resilience Assessment Methodologies. Computer 56 (2) (2023)
André Martins Pio de Mattos, Douglas A. dos Santos, Carolina Imianosky, Douglas R. Melo, Luigi Dilillo
Using HARV-SoC for Reliable Sensing Applications in Radiation Harsh Environments. IWASI (2023)
Douglas A. dos Santos, André Martins Pio de Mattos, Douglas R. Melo, Luigi Dilillo
Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space Environments. DFT (2023)
Wesley Grignani, Douglas A. dos Santos, Luigi Dilillo, Felipe Viel, Douglas R. Melo
A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression. DFT (2023)
Benjamin W. Mezger, Douglas A. dos Santos, Luigi Dilillo, Douglas R. Melo
Hardening a Real-Time Operating System for a Dependable RISC-V System-on-Chip. DFT (2023)
Carolina Imianosky, Douglas A. dos Santos, Douglas R. Melo, Felipe Viel, Luigi Dilillo
Implementation and Reliability Evaluation of a RISC-V Vector Extension Unit. DFT (2023)
Benjamin W. Mezger, Douglas A. dos Santos, Luigi Dilillo, Cesar A. Zeferino, Douglas R. Melo
A Survey of the RISC-V Architecture Software Support. IEEE Access 10 (2022)
Lucas Matana Luza, Annachiara Ruospo, Daniel Söderström, Carlo Cazzaniga, Maria Kastriotou, Ernesto Sánchez, Alberto Bosio, Luigi Dilillo
Emulating the Effects of Radiation-Induced Soft-Errors for the Reliability Assessment of Neural Networks. IEEE Trans. Emerg. Top. Comput. 10 (4) (2022)
Douglas A. dos Santos, André Martins Pio de Mattos, Lucas M. Luza, Carlo Cazzaniga, Maria Kastriotou, Douglas R. Melo, Luigi Dilillo
Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip. DFT (2022)
Lucas Matana Luza, Frederic Wrobel, Luis Entrena, Luigi Dilillo
Impact of Atmospheric and Space Radiation on Sensitive Electronic Devices. ETS (2022)
Annachiara Ruospo, Lucas Matana Luza, Alberto Bosio, Marcello Traiola, Luigi Dilillo, Ernesto Sánchez
Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks. LATS (2021)
Lucas Matana Luza, Annachiara Ruospo, Alberto Bosio, Ernesto Sánchez, Luigi Dilillo
A Model-Based Framework to Assess the Reliability of Safety-Critical Applications. DDECS (2021)
Douglas A. dos Santos, Lucas M. Luza, Maria Kastriotou, Carlo Cazzaniga, Cesar A. Zeferino, Douglas R. Melo, Luigi Dilillo
Characterization of a RISC-V System-on-Chip under Neutron Radiation. DTIS (2021)
Lucas Matana Luza, Daniel Söderström, André Martins Pio de Mattos, Eduardo Augusto Bezerra, Carlo Cazzaniga, Maria Kastriotou, Christian Poivey, Luigi Dilillo
Technology Impact on Neutron-Induced Effects in SDRAMs: A Comparative Study. DTIS (2021)
Douglas Rossi Melo, César Albenes Zeferino, Eduardo Augusto Bezerra, Luigi Dilillo
Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router. DTIS (2021)
Lucas Matana Luza, Daniel Söderström, Helmut Puchner, Rubén García Alía, Manon Letiche, Alberto Bosio, Luigi Dilillo
Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM. DTIS (2020)
Lucas Matana Luza, Daniel Söderström, Georgios Tsiligiannis, Helmut Puchner, Carlo Cazzaniga, Ernesto Sánchez, Alberto Bosio, Luigi Dilillo
Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems. DFT (2020)
Douglas Almeida dos Santos, Lucas Matana Luza, César Albenes Zeferino, Luigi Dilillo, Douglas Rossi de Melo
A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems. DTIS (2020)
Iacopo Fara, Lucas Matana Luza, Jérôme Boch, Gianluca Furano, Marco Ottavi, Luigi Dilillo
Design and Implementation of a Flexible Interface for TID Detector. IWASI (2019)
Cezar Antônio Rigo, Lucas M. Luza, Elder Dominghini Tramontin, Victor M. Goncalves Martins, Sara Vega Martínez, Leonardo Kessler Slongo, Laio Oriel Seman, Luigi Dilillo, Fabian Luis Vargas, Eduardo A. Bezerra
A Fault-Tolerant Reconfigurable Platform for Communication Modules of Satellites. LATS (2019)
Douglas Rossi de Melo, César Albenes Zeferino, Luigi Dilillo, Eduardo Augusto Bezerra
Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router. LATS (2019)
Douglas R. Melo, Cesar A. Zeferino, Luigi Dilillo, Eduardo A. Bezerra
Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design. Sensors 19 (24) (2019)
Dario Asciolla, Luigi Dilillo, Douglas A. dos Santos, Douglas R. Melo, Alessandra Menicucci, Marco Ottavi
Characterization of a RISC-V Microcontroller Through Fault Injection. ApplePies (2019)
Lucas Matana Luza, Alexandre Besser, Viyas Gupta, Arto Javanainen, Ali Mohammadzadeh, Luigi Dilillo
Effects of Heavy Ion and Proton Irradiation on a SLC NAND Flash Memory. DFT (2019)
Emna Farjallah, Valentin Gherman, Jean-Marc Armani, Luigi Dilillo
Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells. DTIS (2018)
Marcelino Seif, Emna Farjallah, Franck Badets, Emna Chabchoub, Christophe Layer, Jean-Marc Armani, Francis Joffre, Costin Anghel, Luigi Dilillo, Valentin Gherman
Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps. ETS (2017)
Valentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo
Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics. ITC (2017)
Frederic Wrobel, Antoine D. Touboul, Vincent Pouget, Luigi Dilillo, Jerome Boch, Frédéric Saigné
A calculation method to estimate single event upset cross section. Microelectron. Reliab. (2017)
Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo Bonet Zordan
An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED (2016)
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot
Design for Test and Diagnosis of Power Switches. J. Circuits Syst. Comput. 25 (3) (2016)
Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard
An effective hybrid fault-tolerant architecture for pipelined cores. ETS (2015)
Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
An effective ATPG flow for Gate Delay Faults. DTIS (2015)
Luigi Dilillo, Alexandre Bosser, Viyas Gupta, Frederic Wrobel, Frédéric Saigné
Real-time SRAM based particle detector. IWASI (2015)
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Debaud, S. Guilhot
Design-for-Diagnosis Architecture for Power Switches. DDECS (2015)
Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
Scan-chain intra-cell defects grading. DTIS (2015)
Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
Exploring the impact of functional test programs re-used for power-aware testing. DATE (2015)
Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch
An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI (2015)
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot
Test and diagnosis of power switches. DDECS (2014)
D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. 30 (4) (2014)
Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray
Intra-Cell Defects Diagnosis. J. Electron. Test. 30 (5) (2014)
Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray
On the Generation of Diagnostic Test Set for Intra-cell Defects. ATS (2014)
Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS (2014)
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot
iBoX - Jitter based Power Supply Noise sensor. ETS (2014)
Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Paolo Bernardi
A Comprehensive Evaluation of Functional Programs for Power-Aware Test. NATW (2014)
Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI (2014)
Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
Timing-aware ATPG for critical paths with multiple TSVs. DDECS (2014)
Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS (2014)
Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC (2014)
Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Herault, Ken Mackay
A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. IEEE Trans. Very Large Scale Integr. Syst. 22 (11) (2014)
Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
TSV aware timing analysis and diagnosis in paths with multiple TSVs. VTS (2014)
Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi
An intra-cell defect grading tool. DDECS (2014)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil Badereddine
On the Test and Mitigation of Malfunctions in Low-Power SRAMs. J. Electron. Test. 30 (5) (2014)
Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. Asian Test Symposium (2013)
Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS (2013)
Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. DTIS (2013)
Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Miroslav Valka, Patrick Girard
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption. J. Low Power Electron. 9 (2) (2013)
Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. NEWCAS (2013)
Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. 21 (5) (2013)
Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. ITC (2013)
Elena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS (2013)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
Test solution for data retention faults in low-power SRAMs. DATE (2013)
Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, J.-R. Vaillé, Frederic Wrobel, Frédéric Saigné
Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI (2013)
Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
Computing detection probability of delay defects in signal line tsvs. ETS (2013)
Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. ETS (2013)
Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Etienne Auvray
Effect-cause intra-cell diagnosis at transistor level. ISQED (2013)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
A built-in scheme for testing and repairing voltage regulators of low-power srams. VTS (2013)
Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel
Why and How Controlling Power Consumption during Test: A Survey. Asian Test Symposium (2012)
Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay
Coupling-based resistive-open defects in TAS-MRAM architectures. ETS (2012)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
Defect analysis in power mode control logic of low-power SRAMs. ETS (2012)
Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Advanced test methods for SRAMs. VTS (2012)
Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Antoine D. Touboul, Frederic Wrobel, Frédéric Saigné
Evaluation of test algorithms stress effect on SRAMs under neutron radiation. IOLTS (2012)
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electron. Test. 28 (3) (2012)
Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
eFlash Memories. J. Electron. Test. 28 (2) (2012)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
Low-power SRAMs power mode control logic: Failure analysis and test solutions. ITC (2012)
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, P. Debaud, S. Guilhot
Power Supply Noise Sensor Based on Timing Uncertainty Measurements. Asian Test Symposium (2012)
Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay
Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. Asian Test Symposium (2012)
Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Patrick Girard, Miroslav Valka
Peak Power Estimation: A Case Study on CPU Cores. Asian Test Symposium (2012)
Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay
Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE (2012)
Carolina Metzler, Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
Through-Silicon-Via resistive-open defect analysis. ETS (2012)
D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich
A pseudo-dynamic comparator for error detection in fault tolerant architectures. VTS (2012)
Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium (2011)
Jean Marc Gallière, Luigi Dilillo
Versatile march test generator for hands-on memory testing laboratory. MSE (2011)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine
Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium (2011)
Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS (2011)
Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT (2011)
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
On using address scrambling to implement defect tolerance in SRAMs. ITC (2011)
Luigi Dilillo, Paolo Rech, Jean Marc Gallière, Patrick Girard, Frederic Wrobel, Frédéric Saigné
Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench. LATW (2011)
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS (2011)
D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium (2011)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS (2011)
Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, Xiaoqing Wen
Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium (2011)
Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS (2011)
Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
eFlash memory technology for defect injection and faulty behavior prediction. ETS (2010)
Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed
Is test power reduction through X-filling good enough? ITC (2010)
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
A statistical simulation method for reliability analysis of SRAM core-cells. DAC (2010)
Paolo Rech, Michelangelo Grosso, Fabio Melchiori, D. Loparco, Davide Appello, Luigi Dilillo, Alessandro Paccagnella, Matteo Sonza Reorda
Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts. IOLTS (2010)
Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo
A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium (2010)
Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium (2010)

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Publication Activity (10 Years)

Top Topics

Top Venues

Luigi Dilillo