Valentin Gherman

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 8

Top Topics

Top Venues

J. Electron. Test.

Publications

Valentin Gherman, Cyrille Laffond
Sequential Decoders for Binary Linear Block ECCs. VTS (2024)
Bastien Giraud, S. Ricavy, Yasser Moursy, C. Laffond, I. Sever, Valentin Gherman, M. Pezzin, F. Lepin, M. Diallo, K. Zenati, S. Dumas, M. Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noël, A. Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas
Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro. IMW (2023)
Valentin Gherman, Samuel Evain, Bastien Giraud
Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities. DATE (2020)
Bastien Deveautour, Arnaud Virazel, Patrick Girard, Valentin Gherman
On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits. J. Electron. Test. 36 (1) (2020)
Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman
Is aproximate computing suitable for selective hardening of arithmetic circuits? DTIS (2018)
Emna Farjallah, Valentin Gherman, Jean-Marc Armani, Luigi Dilillo
Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells. DTIS (2018)
Marcelino Seif, Emna Farjallah, Franck Badets, Emna Chabchoub, Christophe Layer, Jean-Marc Armani, Francis Joffre, Costin Anghel, Luigi Dilillo, Valentin Gherman
Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps. ETS (2017)
Valentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo
Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics. ITC (2017)
Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner, Valentin Gherman
Shadow-scan design with low latency overhead and in-situ slack-time monitoring. ETS (2014)
Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Lirida Alves de Barros Naviner, Valentin Gherman
Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths. IOLTS (2014)
Samuel Evain, Valentin Savin, Valentin Gherman
Error Correction Schemes with Erasure Information for Fast Memories. J. Electron. Test. 30 (2) (2014)
Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection. DATE (2013)
Valentin Gherman, Samuel Evain, Yannick Bonhomme
Memory Reliability Improvement Based on Maximized Error-Correcting Codes. J. Electron. Test. 29 (4) (2013)
Samuel Evain, Valentin Gherman
Error-correction schemes with erasure information for fast memories. ETS (2013)
Valentin Gherman, Samuel Evain, Yannick Bonhomme
Memory reliability improvements based on maximized error-correcting codes. ETS (2012)
Valentin Gherman, J. Massas, Samuel Evain, Stéphane Chevobbe, Yannick Bonhomme
Error prediction based on concurrent self-test and reduced slack time. DATE (2011)
Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme
Programmable extended SEC-DED codes for memory errors. VTS (2011)
Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme
Generalized parity-check matrices for SEC-DED codes with fixed parity. IOLTS (2011)
Samuel Evain, Yannick Bonhomme, Valentin Gherman
Programmable restricted SEC codes to mask permanent faults in semiconductor memories. IOLTS (2010)
Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme
System-level hardware-based protection of memories against soft-errors. DATE (2009)
Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers
Deterministic logic BIST for transition fault testing. IET Comput. Digit. Tech. 1 (3) (2007)
Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers
Synthesis of irregular combinational functions with large don't care sets. ACM Great Lakes Symposium on VLSI (2007)
Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers
Deterministic Logic BIST for Transition Fault Testing. ETS (2006)
Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel
Implementing a Scheme for External Deterministic Self-Test. VTS (2005)
Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers
Efficient Pattern Mapping for Deterministic Logic BIST. ITC (2004)