Jürgen Schlöffel

Publication Activity (10 Years)

Years Active: 2000-2012
Publications (10 Years): 0

Top Topics

False Positive And False Negative

Statistical Significance

Reduction Method

Database Workloads

Top Venues

Publications

Friedrich Hapke, Michael Reese, Jason Rivers, A. Over, V. Ravikumar, Wilfried Redemund, Andreas Glowatz, Jürgen Schlöffel, Janusz Rajski
Cell-aware Production test results from a 32-nm notebook processor. ITC (2012)
Friedrich Hapke, Jürgen Schlöffel
Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates. ETS (2012)
Friedrich Hapke, Jürgen Schlöffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, J. Rearick, Jason Rivers
Cell-aware analysis for small-delay effects and production test results from different fault models. ITC (2011)
Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. ETS (2010)
Friedrich Hapke, Wilfried Redemund, Jürgen Schlöffel, Rene Krenz-Baath, Andreas Glowatz, Michael Wittke, Hamidreza Hashempour, Stefan Eichenberger
Defect-oriented cell-internal testing. ITC (2010)
Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electron. Test. 26 (3) (2010)
Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian
SUPERB: Simulator utilizing parallel evaluation of resistive bridges. ACM Trans. Design Autom. Electr. Syst. 14 (4) (2009)
Friedrich Hapke, Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel, Hamidreza Hashempour, Stefan Eichenberger, Camelia Hora, Dan Adolfsson
Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs. ITC (2009)
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it Inf. Technol. 51 (2) (2009)
Abdul Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Jürgen Schlöffel, Friedrich Hapke, Andreas Glowatz
Restrict Encoding for Mixed-Mode BIST. VTS (2009)
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille
On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (7) (2008)
Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker
Resistive Bridging Fault Simulation of Industrial Circuits. DATE (2008)
Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL (2007)
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE (2007)
Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Christian G. Zoellin, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Laurent Souef
Programmable deterministic Built-In Self-Test. ITC (2007)
Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers
Deterministic logic BIST for transition fault testing. IET Comput. Digit. Tech. 1 (3) (2007)
Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel
Computation and Application of Absolute Dominators in Industrial Designs. ETS (2007)
Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers
Synthesis of irregular combinational functions with large don't care sets. ACM Great Lakes Symposium on VLSI (2007)
Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers
Deterministic Logic BIST for Transition Fault Testing. ETS (2006)
Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
Fault detection and diagnosis with parity trees for space compaction of test responses. DAC (2006)
Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke
X-masking during logic BIST and its impact on defect coverage. IEEE Trans. Very Large Scale Integr. Syst. 14 (2) (2006)
Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. ISVLSI (2005)
Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel
ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. VLSI Design (2005)
Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel
Implementing a Scheme for External Deterministic Self-Test. VTS (2005)
Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. Asian Test Symposium (2005)
Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel
Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. DFT (2004)
Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel
PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. PATMOS (2000)