Walter Anheier

Publication Activity (10 Years)

Years Active: 1993-2016
Publications (10 Years): 1

Top Topics

Correlation Analysis

Built In Self Test

Physical Design

Top Venues

J. Circuits Syst. Comput.

Publications

Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier
Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim. J. Circuits Syst. Comput. 25 (3) (2016)
Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier
TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms. DDECS (2015)
Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier
Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults. VLSI Design (2010)
Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier
Fault diagnosis of crosstalk induced glitches and delay faults. DDECS (2010)
Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler
Timing Arc based logic analysis for false noise reduction. ICCAD (2009)
Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
Crosstalk fault modeling in defective pair of interconnects. Integr. 41 (1) (2008)
Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. ISQED (2008)
Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects. DDECS (2007)
Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
Modeling of Crosstalk Fault in Defective Interconnects. PATMOS (2006)
Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. DFT (2006)
Sascha Kneip, Walter Anheier
Vergleich und Optimierung von Algorithmen zur Modulo-Multiplikation auf Smartcards. MBMV (2006)
Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier
Reduction of Crosstalk Pessimism using Tendency Graph Approach. ICCD (2006)
Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel
ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. VLSI Design (2005)
Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. Asian Test Symposium (2005)
Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel
Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. DFT (2004)
Ajoy Kumar Palit, Gerhard Doeding, Walter Anheier, Dobrivoje Popovic
Backpropagation based training algorithm for Takagi-Sugeno type MIMO neuro-fuzzy network to forecast electrical load time series. FUZZ-IEEE (2002)
Volker Meyer, Walter Anheier, Arne Sticht
Non-robust delay test pattern enhancement. ICECS (2002)
Badreddine Rejeb, Heiko Henkelmann, Walter Anheier
Integer division in residue number system. ICECS (2001)
Michael Fischell, Walter Anheier
Investigations of on-line/off-line tests for sensors. ICECS (2001)
Volker Meyer, Walter Anheier, Arne Sticht
Non-robust delay test pattern generation based on stuck-at TPG. ICECS (2001)
A. Schubert, Walter Anheier
On Random Pattern Testability of Cryptographic VLSI Cores. J. Electron. Test. 16 (3) (2000)
A. Schubert, Walter Anheier
On random pattern testability of cryptographic VLSI cores. ETW (1999)
A. Schubert, Walter Anheier
Efficient VLSI implementation of modern symmetric block ciphers. ICECS (1999)
Heiko Henkelmann, Walter Anheier
Implementation of sign detection in RNS using mixed radix representation. ICECS (1999)
Frank Poehl, Walter Anheier
Quality Determination for Gate Delay Fault Tests Considering Three-State Elements. J. Electron. Test. 14 (1-2) (1999)
Heiko Henkelmann, C. Bruennlein, Walter Anheier
Effiziente Methoden zum Zahlenvergleich und zur Vorzeichenerkennung in Restklassensystemen. MBMV (1999)
Ansgar Drolshagen, Walter Anheier, C. Chandra Sekhar
A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech Signal. VLSI Design (1998)
Ansgar Drolshagen, Heiko Henkelmann, Walter Anheier
Processor Elements for the Standard Cell Implementation of Residue Number Systems. ASAP (1997)
Stefan Radtke, Jens Bargfrede, Walter Anheier
Distributed automatic test pattern generation with a parallel FAN algorithm. ICCD (1995)
Beom-Ik Cheon, Walter Anheier, Rainer Laur
A New Strategy for Test Pattern Generation in Sequential Circuits. ISCAS (1994)
Norbert Ebi, Bernd Lauterbach, Walter Anheier
An image analysis system for automatic data acquisition from colored scanned maps. Mach. Vis. Appl. 7 (3) (1994)
Bernd Lauterbach, Walter Anheier
Segmentation of Scanned Maps in Uniform Color Spaces. MVA (1994)
B. Lauerbach, Walter Anheier
Segmentierung farbiger kartographischer Vorlagen in empfindungsgemäßen Farbräumen. DAGM-Symposium (1993)