ETW

Keyphrases

Publications

2003

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
Requirements for delay testing of look-up tables in SRAM-based FPGAs. ETW (2003)
Said Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. van de Goor
Importance of dynamic faults for new SRAM technologies. ETW (2003)
Alessandra Fudoli, Alberto Ascagni, Davide Appello, Hans A. R. Manhaeve
test strategies for deep submicron production test application. Experiences and targets from the field. ETW (2003)
8th European Test Workshop, ETW 2003, Maastricht, The Netherlands, May 25-28, 2003 ETW (2003)
Ozgur Sinanoglu, Alex Orailoglu
Parity-based output compaction for core-based SOCs [logic testing]. ETW (2003)
Helmut Lang, Bhuwnesh Pande, Heiko Ahrens
Automating test program generation in STIL - expectations and experiences using IEEE 1450 [standard test interface language]. ETW (2003)
Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, R. Rodriguez, Joan Figueras
On the selection of efficient arithmetic additive test pattern generators [logic test]. ETW (2003)
H. J. Vermaak, H. G. Kerkhoff
Enhanced P1500 compliant wrapper suitable for delay fault testing of embedded cores. ETW (2003)
Marco Rona, Gunter Krampl, Fritz Raczkowski
Automating the device interface board modeling for virtual test. ETW (2003)
Eric Liau, Doris Schmitt-Landsiedel
Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits. ETW (2003)
Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
Modeling feedback bridging faults with non-zero resistance. ETW (2003)
M. J. Geuzebroek, Ad J. van de Goor
TPI for improving PR fault coverage of Boolean and three-state circuits. ETW (2003)
Anuja Sehgal, Aishwarya Dubey, Erik Jan Marinissen, Clemens Wouters, Harald P. E. Vranken, Krishnendu Chakrabarty
Yield analysis for repairable embedded memories. ETW (2003)
Erik Moerman, Sébastien Bocq, Johan Verfaillie
Debug architecture for system on chip taking full advantage of the test access port. ETW (2003)
Timm Ostermann, Bernd Deutschmann
Characterization of the EME of integrated circuits with the help of the IEC standard 61967 [electromagnetic emission]. ETW (2003)
Sandeep Kumar Goel, Erik Jan Marinissen
Control-aware test architecture design for modular SOC testing. ETW (2003)
Marten Seth
RF ATE equipment benefit from advanced network analyzer technology. ETW (2003)
Daniel Arumí-Delgado, Rosa Rodríguez-Montañés, José Pineda de Gyvez, Guido Gronthoud
and weak-open defects. ETW (2003)
Fulvio Corno, Giovanni Squillero, Matteo Sonza Reorda
Code generation for functional validation of pipelined microprocessors. ETW (2003)
Simone Borri, Magali Hage-Hassan, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Defect-oriented dynamic fault models for embedded-SRAMs. ETW (2003)
Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
On path selection for delay fault testing considering operating conditions [logic IC testing]. ETW (2003)
Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, Bruno Rouzeyre
An efficient approach to SoC wrapper design, TAM configuration and test scheduling. ETW (2003)
Victor Avendaño, Víctor H. Champac, Joan Figueras
Signal integrity loss in bus lines due to open shielding defects. ETW (2003)
Octavian Petre, Hans G. Kerkhoff
Scan test strategy for asynchronous-synchronous interfaces [SoC testing]. ETW (2003)

2002

2001