Kishore K. Duganapalli

Publication Activity (10 Years)

Years Active: 2005-2016
Publications (10 Years): 1

Top Topics

Correlation Analysis

Built In Self Test

Physical Design

Top Venues

J. Circuits Syst. Comput.

Publications

Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier
Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim. J. Circuits Syst. Comput. 25 (3) (2016)
Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier
TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms. DDECS (2015)
Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
Crosstalk fault modeling in defective pair of interconnects. Integr. 41 (1) (2008)
Shyam Praveen Vudathu, Kishore K. Duganapalli, Rainer Laur, D. Kubalinska, Angelika Bunse-Gerstner
Parametric Yield Analysis of Mems via Statistical Methods CoRR (2007)
Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects. DDECS (2007)
Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
Modeling of Crosstalk Fault in Defective Interconnects. PATMOS (2006)
Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. DFT (2006)
Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. Asian Test Symposium (2005)