Manfred Glesner

Publication Activity (10 Years)

Years Active: 1986-2017
Publications (10 Years): 1

Top Venues

ACM Trans. Embed. Comput. Syst.

FPL

ESSCIRC

VLSI-SoC (Selected Papers)

Publications

Ricardo Reis, Manfred Glesner
VLSI-SoC: An Enduring Tradition. VLSI-SoC (Selected Papers) (2017)
François Philipp, Manfred Glesner
High-level abstraction for teaching smart systems design with modular hardware. EWME (2014)
François Philipp, Manfred Glesner
An event-based middleware for the remote management of runtime hardware reconfiguration. FPL (2013)
Luciano Ost, Marcelo Mandelli, Gabriel Marchesan Almeida, Leandro Möller, Leandro Soares Indrusiak, Gilles Sassatelli, Pascal Benoit, Manfred Glesner, Michel Robert, Fernando Moraes
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach. ACM Trans. Embed. Comput. Syst. 12 (3) (2013)
Manfred Glesner, François Philipp
Embedded systems design for smart system integration. ISVLSI (2013)
Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
Runtime Contention and Bandwidth-Aware Adaptive Routing Selection Strategies for Networks-on-Chip. IEEE Trans. Parallel Distributed Syst. 24 (7) (2013)
Ramkumar Ganesan, Jürgen Krumm, Sebastian Pankalla, Klaus Ludwig, Manfred Glesner
Design of an organic electronic label on a flexible substrate for temperature sensing. ESSCIRC (2013)
D. Erdenechimeg, Ts. Sugir, François Philipp, Manfred Glesner
Implementation and outcomes of FPGA-based system design in Mongolian education. FPL (2012)
Élvio Carlos Dutra e Silva Júnior, Leandro Soares Indrusiak, Weiler Alves Finamore, Manfred Glesner
A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme. Int. J. Reconfigurable Comput. 2012 (2012)
Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method. Microprocess. Microsystems 36 (6) (2012)
Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
Erratum to Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method Microprocessors and Microsystems (2012) 449-461. Microprocess. Microsystems 36 (6) (2012)
François Philipp, Conrad Klytta, Manfred Glesner, Élvio Dutra
Hardware acceleration of combined cipher and forward error correction for low-power wireless applications. ReCoSoC (2012)
François Philipp, Manfred Glesner
: A graphical tool for the generation of configuration bitstreams for a smart sensor interface based on a Coarse-Grained Dynamically Reconfigurable Architecture. FPL (2012)
Leandro Möller, Leandro Soares Indrusiak, Luciano Ost, Fernando Gehm Moraes, Manfred Glesner
Comparative analysis of dynamic task mapping heuristics in heterogeneous NoC-based MPSoCs. ISSoC (2012)
François Philipp, Faizal Arya Samman, Manfred Glesner
Design of an autonomous platform for distributed sensing-actuating systems. International Symposium on Rapid System Prototyping (2011)
Thomas Hollstein, Faizal Arya Samman, Ashok Jaiswal, Haoyuan Ying, Manfred Glesner, Klaus Hofmann
Invited paper: Design criteria for dependable System-on-Chip architectures. ReCoSoC (2011)
Surapong Pongyupinpanich, Manfred Glesner
On-chip efficient Round-Robin scheduler for high-speed interconnection. International Symposium on Rapid System Prototyping (2011)
Luciano Ost, Marcelo Mandelli, Gabriel Marchesan Almeida, Leandro Soares Indrusiak, Leandro Möller, Manfred Glesner, Gilles Sassatelli, Michel Robert, Fernando Moraes
Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework. SBCCI (2011)
François Philipp, Manfred Glesner
Mechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor Node. FPL (2011)
Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip. Microprocess. Microsystems 35 (3) (2011)
Ping Zhao, Manfred Glesner
RF energy harvester design with autonomously adaptive impedance matching network based on auxiliary charge-pump rectifier. ISCAS (2011)
Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-Chip. IEEE Trans. Parallel Distributed Syst. 22 (4) (2011)
Surapong Pongyupinpanich, Manfred Glesner
Pipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDIC. FPL (2011)
Faizal Arya Samman, François Philipp, Manfred Glesner
Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems. CHANGE@ASPLOS (2011)
François Philipp, Manfred Glesner
A Multi-level Reconfigurable Architecture for a Wireless Sensor Node Coprocessing Unit. IPDPS Workshops (2011)
Faizal Arya Samman, Surapong Pongyupinpanich, Manfred Glesner
Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems. ReCoSoC (2011)
Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 18 (7) (2010)
Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Manfred Glesner, Fernando Gehm Moraes, Jari Nurmi
A case study of hierarchically heterogeneous application modelling using UML and Ptolemy II. SoC (2010)
Élvio Dutra, Manfred Glesner, Weiler Alves Finamore, Leandro Soares Indrusiak
Novel method of chaotic systems evaluation for implementations of encryption algorithms. ICT (2010)
Leandro Möller, Peter Fischer, Fernando Moraes, Leandro Soares Indrusiak, Manfred Glesner
Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers. FPL (2010)
Leandro Möller, André Rodrigues, Fernando Moraes, Leandro Soares Indrusiak, Manfred Glesner
Instruction Set Simulator for MPSoCs based on NoCs and MIPS Processors. ReCoSoC (2010)
Sanna Määttä, Leandro Möller, Leandro Soares Indrusiak, Luciano Ost, Manfred Glesner, Jari Nurmi, Fernando Moraes
Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms. Int. J. Embed. Real Time Commun. Syst. 1 (1) (2010)
Heiko Hinkelmann, Peter Zipf, Jia Li, Guifang Liu, Manfred Glesner
On the design of reconfigurable multipliers for integer and Galois field multiplication. Microprocess. Microsystems 33 (1) (2009)
Andre Guntoro, Manfred Glesner
A flexible floating-point wavelet transform and wavelet packet processor. DATE (2009)
Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Manfred Glesner, Fernando Gehm Moraes, Jari Nurmi
Characterising embedded applications using a UML profile. SoC (2009)
Alberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner
Low-Power Coding for Networks-on-Chip with Virtual Channels. J. Low Power Electron. 5 (1) (2009)
Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. FPL (2009)
Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf
Towards a unique FPGA-based identification circuit using process variations. FPL (2009)
Petru Bogdan Bacinschi, Manfred Glesner
A Multistep Extrapolated S-Parameter Model for Arbitrary On-Chip Interconnect Structures. VLSI-SoC (2009)
Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management. VLSI Design 2009 (2009)
Kurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak, Manfred Glesner
Providing Memory Management Abstraction for Self-Reconfigurable Video Processing Platforms. Int. J. Reconfigurable Comput. 2009 (2009)
Heiko Hinkelmann, Peter Zipf, Manfred Glesner
Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes. FPL (2009)
Thomas C. P. Chau, S. Man Ho Ho, Philip Heng Wai Leong, Peter Zipf, Manfred Glesner
Generation of Synthetic Floating-Point benchmark circuits. IPDPS (2009)
Peter Zipf, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, Manfred Glesner
A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips. Int. J. Reconfigurable Comput. 2009 (2009)
Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner
Process variations aware robust on-chip bus architecture synthesis for MPSoCs. ISCAS (2008)
Andre Guntoro, Manfred Glesner
Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters. ASAP (2008)
Andre Guntoro, Manfred Glesner
A Flexible Floating-Point Wavelet Processor. SITIS (2008)
Massoud Momeni, Andre Guntoro, Hans-Peter Keil, Manfred Glesner
Impact of circuit nonidealities on the implementation of switched-capacitor resonators. APCCAS (2008)
Heiko Hinkelmann, Peter Zipf, Manfred Glesner
A scalable reconfiguration mechanism for fast dynamic reconfiguration. FPT (2008)
Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
Coarse-grained reconfiguration. FPL (2008)
Enkhbold Ochirsuren, Heiko Hinkelmann, Leandro Soares Indrusiak, Manfred Glesner
TinyOS Extensions for a Wireless Sensor Network Node Based on a Dynamically Reconfigurable Processor. DIPES (2008)
Peter Zipf, Heiko Hinkelmann, Hui Shao, Radu Dogaru, Manfred Glesner
An area-efficient FPGA realisation of a codebook-based image compression method. FPT (2008)
Andre Guntoro, Massoud Momeni, Hans-Peter Keil, Manfred Glesner
High-performance floating-point VLSI architecture of lifting-based forward and inverse wavelet transforms. APCCAS (2008)
Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Fernando Moraes, Manfred Glesner
Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects. ISVLSI (2008)
Petru Bogdan Bacinschi, Tudor Murgan, Klaus Koch, Manfred Glesner
An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs. DATE (2008)
Hans-Peter Keil, Massoud Momeni, Andre Guntoro, Alberto García Ortiz, Manfred Glesner
A novel leakage-estimation method for input-vector control. APCCAS (2008)
Luciano Ost, Fernando Gehm Moraes, Leandro Möller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Määttä, Jari Nurmi
A simplified executable model to evaluate latency and throughput of networks-on-chip. SBCCI (2008)
Andre Guntoro, Manfred Glesner
High-performance fpga-based floating-point adder with three inputs. FPL (2008)
Andre Guntoro, Hans-Peter Keil, Manfred Glesner
High-Speed Configurable VLSI Architecture of a General Purpose Lifting-Based Discrete Wavelet Processor. ICETE (Selected Papers) (2008)
Andre Guntoro, Manfred Glesner
A Lifting-Based Discrete Wavelet Transform and Discrete Wavelet Packet Processor with Support for Higher Order Wavelet Filters. VLSI-SoC (Selected Papers) (2008)
Andre Guntoro, Hans-Peter Keil, Manfred Glesner
Configurable VLSI Architecture of a General Purpose Lifting-based Wavelet Processor. SIGMAP (2008)
Heiko Hinkelmann, Andreas Reinhardt, Manfred Glesner
A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support. IEEE International Workshop on Rapid System Prototyping (2008)
Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Jari Nurmi, Manfred Glesner, Fernando Moraes
Validation of executable application models mapped onto network-on-chip platforms. SIES (2008)
Andre Guntoro, Manfred Glesner
Low-latency VLSI architecture of a 3-input floating-point adder. APCCAS (2008)
Kurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak, Manfred Glesner
Enabling self-reconfiguration on a video processing platform. SIES (2008)
Massoud Momeni, Petru Bogdan Bacinschi, Manfred Glesner
Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation. DATE (2008)
Andre Guntoro, Manfred Glesner
A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor. FPL (2008)
Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
Flexible parallel pipeline network-on-chip based on dynamic packet identity management. IPDPS (2008)
Alberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner
PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels. PATMOS (2008)
Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
Multicast Parallel Pipeline Router Architecture for Network-on-Chip. DATE (2008)
Christopher Spies, Peter Zipf, Manfred Glesner, Harald Klingbeil
Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II. IEEE International Workshop on Rapid System Prototyping (2008)
Radu Dogaru, Manfred Glesner
A fast and compact classifier based on sorting in an iteratively expanded input space. Int. J. Intell. Syst. 23 (5) (2008)
Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll
Application-specific reconfigurable processors. FPL (2008)
Enkhbold Ochirsuren, Leandro Soares Indrusiak, Manfred Glesner
An Actor-Oriented Group Mobility Model for Wireless Ad Hoc Sensor Networks. ICDCS Workshops (2008)
Heiko Hinkelmann, Tudor Murgan, Guifang Liu, Peter Zipf, Manfred Glesner
On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication. ReCoSoC (2007)
Leandro Soares Indrusiak, Andreas Thuy, Manfred Glesner
Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns. DATE (2007)
Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck
Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). it Inf. Technol. 49 (3) (2007)
Leandro Soares Indrusiak, Manfred Glesner
Specification of alternative execution semantics of UML sequence diagrams within actor-oriented models. SBCCI (2007)
Mihail Petrov, Manfred Glesner
An Efficient Fractional-Rate Interpolation Architecture. GLOBECOM (2007)
Peter Zipf, Yang Qiao, Manfred Glesner
Ein Beitrag zur automatischen Erzeugung dynamisch rekonfigurierbarer Hardwarestrukturen. MBMV (2007)
Alberto García Ortiz, Tudor Murgan, Manfred Glesner
Signal Activity Analysis for High-Level Power Estimation in Time-Shared Linear Systems. J. Low Power Electron. 3 (2) (2007)
Tudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner
On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. PATMOS (2007)
Kurt Franz Ackermann, Leandro Soares Indrusiak, Manfred Glesner
System Level Design of a Dynamically Self-Reconfigurable Image Processing System. ReCoSoC (2007)
Sujan Pandey, Manfred Glesner
Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. IEEE Trans. Very Large Scale Integr. Syst. 15 (10) (2007)
Leandro Soares Indrusiak, Manfred Glesner, Ricardo Reis
On the Evolution of Remote Laboratories for Prototyping Digital Electronic Systems. IEEE Trans. Ind. Electron. 54 (6) (2007)
Tudor Murgan, Andre Guntoro, Heiko Hinkelmann, Petru Bogdan Bacinschi, Manfred Glesner
Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling. ReCoSoC (2007)
Mihail Petrov, Manfred Glesner
A Scalable Resampling Architecture. GLOBECOM (2007)
José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Ricardo Reis, Manfred Glesner
Reducing the Power Consumption in Networks-on-Chip through Data Coding Schemes. ICECS (2007)
Thomas Hollstein, Manfred Glesner
Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms. Comput. Electr. Eng. 33 (4) (2007)
José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
Inserting Data Encoding Techniques into NoC-Based Systems. ISVLSI (2007)
Heiko Hinkelmann, Peter Zipf, Manfred Glesner
A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks. FPT (2007)
Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. Noll
A Power Estimation Model for an FPGA-based Softcore Processor. FPL (2007)
Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner
A Customizable LEON2-Based VLIW Processor. ReCoSoC (2007)
Romualdo Begale Prudencio, Leandro Soares Indrusiak, Manfred Glesner
An Efficient Hardware Implementation of a Self-Adaptable Equalizer for WCDMA Downlink UMTS Standard. ISVLSI (2006)
Tudor Murgan, Oliver Mitea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. VLSI-SoC (2006)
Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner
A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects. ICCAD (2006)
Andreas Thuy, Leandro Soares Indrusiak, Manfred Glesner
Applying Communication Patterns to Actor-Oriented Models. FDL (2006)
Heiko Hinkelmann, Peter Zipf, Manfred Glesner
A metric for the energy-efficiency of dynamically reconfigurable systems. ARCS Workshops (2006)
Sujan Pandey, Manfred Glesner
Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique. ISCAS (2006)
Peter Zipf, Volker Hampel, Manfred Glesner, Thilo Pionteck
Eine Scheduling Heuristik zur Minimierung der Verlustleistung. MBMV (2006)

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Publication Activity (10 Years)

Top Topics

Top Venues

Manfred Glesner