Dmitrij Kissler

Publication Activity (10 Years)

Years Active: 2006-2011
Publications (10 Years): 0

University of Erlangen-Nuremberg (PHD)

Education History

University of Erlangen-Nuremberg

PHD

Publications

Dmitrij Kissler, D. Gran, Zoran Salcic, Frank Hannig, Jürgen Teich
Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays. IEEE Embed. Syst. Lett. 3 (2) (2011)
Dmitrij Kissler, Frank Hannig, Jürgen Teich
Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays. J. Low Power Electron. 7 (1) (2011)
Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier
A holistic approach for tightly coupled reconfigurable parallel processors. Microprocess. Microsystems 33 (1) (2009)
Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. J. Low Power Electron. 5 (1) (2009)
Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
Coarse-grained reconfiguration. FPL (2008)
Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. PATMOS (2008)
Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA (2007)
Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich
Efficient event-driven simulation of parallel processor architectures. SCOPES (2007)
Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier
Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC (2007)
Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement
Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS (2007)
Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich
Hardware Cost Analysis for Weakly Programmable Processor Arrays. SoC (2006)
Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich
A highly parameterizable parallel processor array architecture. FPT (2006)
Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker
An Architecture Description Language for Massively Parallel Processor Architectures. MBMV (2006)
Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC (2006)
Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich
A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES (2006)

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Publication Activity (10 Years)

Dmitrij Kissler