Jürgen Teich

ORCID

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 230

Top Venues

Saarland University, Germany (PHD)

Education History

Saarland University, Germany

PHD

Publications

Khalil Esper, Jürgen Teich
History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs. NG-RES@HiPEAC (2024)
Martín Letras, Joachim Falk, Jürgen Teich
Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems. IEEE Access 12 (2024)
Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich
Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers. VEHITS (2024)
Khalil Esper, Stefan Wildermann, Jürgen Teich
Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs. DATE (2024)
Mark Deutel, Frank Hannig, Christopher Mutschler, Jürgen Teich
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers. CoRR (2024)
Jens Trautmann, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s. ACM Trans. Reconfigurable Technol. Syst. 17 (2) (2024)
Muhammad Sabih, Batuhan Sesli, Frank Hannig, Jürgen Teich
Accelerating DNNs Using Weight Clustering on RISC-V Custom Functional Units. DATE (2024)
Pierre-Louis Sixdenier, Stefan Wildermann, Jürgen Teich
GRES: Guaranteed Remaining Energy Scheduling of Energy-harvesting Sensors by Quality Adaptation. MECO (2024)
Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich
ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs. DDECS (2024)
Dominik Walter, Marcel Brand, Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich
ALPACA: An Accelerator Chip for Nested Loop Programs. ISCAS (2024)
Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich
OpTC - A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers. CoRR (2024)
Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation. ARC (2024)
Paul Krüger, Stefan Wildermann, Jürgen Teich
CRESTS: Chronology-based Reconstruction for Side-Channel Trace Segmentation for XTS-AES on Complex Targets. EuroSec@EUROSYS (2024)
Christian Heidorn, Muhammad Sabih, Nicolai Meyerhöfer, Christian Schinabeck, Jürgen Teich, Frank Hannig
Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks. Int. J. Parallel Program. 52 (1-2) (2024)
Alberto Bosio, Mario Barbareschi, Alessandro Savino, Jie Han, Jürgen Teich
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems. IEEE Des. Test 40 (3) (2023)
Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. CASES (2023)
Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations. CoRR (2023)
Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich
An FPGA Avro Parser Generator for Accelerated Data Stream Processing. BTW (2023)
Martín Letras, Joachim Falk, Jürgen Teich
Exploring Multi-Reader Buffers and Channel Placement during Dataflow Network Mapping to Heterogeneous Many-core Systems. CoRR (2023)
Tobias Hahn, Stefan Wildermann, Jürgen Teich
SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAs. FPL (2023)
Jan Spieck, Stefan Wildermann, Jürgen Teich
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs. ACM Trans. Design Autom. Electr. Syst. 28 (1) (2023)
Jan Spieck, Pierre-Louis Sixdenier, Khalil Esper, Stefan Wildermann, Jürgen Teich
Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers. MEMOCODE (2023)
Chetana Pradhan, Martín Letras, Jürgen Teich
Efficient Table-based Function Approximation on FPGAs Using Interval Splitting and BRAM Instantiation. ACM Trans. Embed. Comput. Syst. 22 (4) (2023)
Pierre-Louis Sixdenier, Stefan Wildermann, Martin Ottens, Jürgen Teich
Seque: Lean and Energy-aware Data Management for IoT Gateways. EDGE (2023)
Khalil Esper, Stefan Wildermann, Jürgen Teich
Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms. ACM Trans. Design Autom. Electr. Syst. 28 (6) (2023)
Khalil Esper, Jan Spieck, Pierre-Louis Sixdenier, Stefan Wildermann, Jürgen Teich
RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs. NG-RES@HiPEAC (2023)
Mark Deutel, Philipp Woller, Christopher Mutschler, Jürgen Teich
Energy-efficient Deployment of Deep Learning Applications on Cortex-M based Microcontrollers using Deep Compression. MBMV (2023)
Martín Letras, Joachim Falk, Jürgen Teich
Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers. NG-RES@HiPEAC (2023)
Muhammad Sabih, Mikail Yayla, Frank Hannig, Jürgen Teich, Jian-Jia Chen
Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods. EuroMLSys@EuroSys (2023)
Mark Deutel, Georgios D. Kontes, Christopher Mutschler, Jürgen Teich
Augmented Random Search for Multi-Objective Bayesian Optimization of Neural Networks. CoRR (2023)
Patrick Plagwitz, Frank Hannig, Jürgen Teich
TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs. FPL (2022)
Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. CoRR (2022)
Jens Trautmann, Jürgen Teich, Stefan Wildermann
Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks. FCCM (2022)
Muhammad Sabih, Frank Hannig, Jürgen Teich
DyFiP: explainable AI-based dynamic filter pruning of convolutional neural networks. EuroMLSys@EuroSys (2022)
Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. FPL (2022)
Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. it Inf. Technol. 64 (3) (2022)
Christian Heidorn, Nicolai Meyerhöfer, Christian Schinabeck, Frank Hannig, Jürgen Teich
Hardware-Aware Evolutionary Filter Pruning. SAMOS (2022)
Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Behnaz Pourmohseni, Stefan Wildermann, Fedor Smirnov, Paul E. Meyer, Jürgen Teich
Task Migration Policy for Thermal-Aware Dynamic Performance Optimization in Many-Core Systems. IEEE Access 10 (2022)
Pierre-Louis Sixdenier, Stefan Wildermann, Daniel Ziegler, Jürgen Teich
SIDAM: A Design Space Exploration Framework for Multi-sensor Embedded Systems Powered by Energy Harvesting. SAMOS (2022)
Chetana Pradhan, Martín Letras, Jürgen Teich
Efficient Table-based Function Approximation on FPGAs using Interval Splitting and BRAM Instantiation. CoRR (2022)
Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Stefan Wildermann, Jürgen Teich
Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. ASHES@CCS (2022)
Khalil Esper, Stefan Wildermann, Jürgen Teich
Multi-Requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study. NG-RES@HiPEAC (2022)
Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann
Real-Time Waveform Matching with a Digitizer at 10 GS/s. CoRR (2022)
Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende
The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurr. Comput. Pract. Exp. 34 (14) (2022)
Franz-Josef Streit, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich
Design and Evaluation of a Tunable PUF Architecture for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15 (1) (2022)
Marcel Brand, Frank Hannig, Oliver Keszöcze, Jürgen Teich
Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview. IEEE Trans. Circuits Syst. II Express Briefs 69 (6) (2022)
Peter Brand, Benjamin Hackenberg, Joachim Falk, Jürgen Teich
Grant Prediction-based Dynamic Power Management for 5G to Reduce Mobile Device Energy Consumption. IWCMC (2022)
Muhammad Sabih, Ashutosh Mishra, Frank Hannig, Jürgen Teich
MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks. IGSC (2022)
Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann
Real-Time Waveform Matching with a Digitizer at 10 GS/s. FPL (2022)
Mark Deutel, Philipp Woller, Christopher Mutschler, Jürgen Teich
Deployment of Energy-Efficient Deep Learning Models on Cortex-M based Microcontrollers using Deep Compression. CoRR (2022)
Tobias Hahn, Stefan Wildermann, Jürgen Teich
Auto-Tuning of Raw Filters for FPGAs. FPL (2022)
Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. CoRR (2022)
Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich
Raw Filtering of JSON Data on FPGAs. CoRR (2022)
Jens Trautmann, Arthur Beckers, Lennert Wouters, Stefan Wildermann, Ingrid Verbauwhede, Jürgen Teich
Semi-Automatic Locating of Cryptographic Operations in Side-Channel Traces. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022 (1) (2022)
Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich
Raw Filtering of JSON Data on FPGAs. DATE (2022)
Jan Spieck, Stefan Wildermann, Jürgen Teich
On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Marcel Brand, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. 33 (14) (2021)
Jürgen Teich, Pouya Mahmoody, Behnaz Pourmohseni, Sascha Roloff, Wolfgang Schröder-Preikschat, Stefan Wildermann
Run-Time Enforcement of Non-functional Program Properties on MPSoCs. A Journey of Embedded and Cyber-Physical Systems (2021)
Dominik Walter, Jürgen Teich
LION: real-time I/O transfer control for massively parallel processor arrays. MEMOCODE (2021)
Peter Brand, Joachim Falk, Tanja Maier, Jürgen Teich
Simulating Realistic IoT Network Traffic Using Similarity-based DSE. CSCI (2021)
Franz-Josef Streit, Paul Krüger, Andreas Becher, Jens Schlumberger, Stefan Wildermann, Jürgen Teich
Choice - A Tunable PUF-Design for FPGAs. FPL (2021)
Martín Letras, Joachim Falk, Jürgen Teich
Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications. MBMV (2021)
Khalil Esper, Stefan Wildermann, Jürgen Teich
Enforcement FSMs: specification and verification of non-functional properties of program executions on MPSoCs. MEMOCODE (2021)
Khalil Esper, Stefan Wildermann, Jürgen Teich
A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems (Invited Paper). NG-RES@HiPEAC (2021)
Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. ACM Trans. Embed. Comput. Syst. 20 (5) (2021)
Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jürgen Teich
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. FPL (2021)
Stefan Groth, Jürgen Teich, Frank Hannig
Efficient Application of Tensor Core Units for Convolving Images. SCOPES (2021)
Peter Brand, Joachim Falk, Eduard Potwigin, Jürgen Teich
Multi-Step Ahead Grant Prediction for Dynamic Power Management in Cellular Modems. ISNCC (2021)
Frank Hannig, Jürgen Teich
Open Source Hardware. Computer 54 (10) (2021)
Marcello Traiola, Jorge Echavarria, Alberto Bosio, Jürgen Teich, Ian O'Connor
Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits. ICCAD (2021)
Armin Schuster, Christian Heidorn, Marcel Brand, Oliver Keszöcze, Jürgen Teich
Design Space Exploration of Time, Energy, and Error Rate Trade-offs for CNNs Using Accuracy-Programmable Instruction Set Processors. PKDD/ECML Workshops (1) (2021)
Jens Schlumberger, Stefan Wildermann, Jürgen Teich
CORSICA: A Framework for Conducting Real-World Side-Channel Analysis. NTMS (2021)
Bo Qiao, Jürgen Teich, Frank Hannig
An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning. IPDPS Workshops (2021)
Martín Letras, Joachim Falk, Tobias Schwarzer, Jürgen Teich
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements. ACM Trans. Design Autom. Electr. Syst. 26 (3) (2021)
Jan Spieck, Stefan Wildermann, Jürgen Teich
Domain-Adaptive Soft Real-Time Hybrid Application Mapping for MPSoCs. MLCAD (2021)
M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig
HipaccVX: wedding of OpenVX and DSL-based code generation. J. Real Time Image Process. 18 (3) (2021)
Muhammad Sabih, Frank Hannig, Jürgen Teich
Fault-Tolerant Low-Precision DNNs using Explainable AI. DSN Workshops (2021)
Lekshmi Beena Gopalakrishnan Nair, Andreas Becher, Stefan Wildermann, Klaus Meyer-Wegener, Jürgen Teich
Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System. Datenbank-Spektrum 21 (1) (2021)
Franz-Josef Streit, Stefan Wildermann, Michael Pschyklenk, Jürgen Teich
Providing Tamper-Secure SoC Updates Through Reconfigurable Hardware. ARC (2021)
Jorge Echavarria, Stefan Wildermann, Jürgen Teich
Approximate Logic Synthesis of Very Large Boolean Networks. DATE (2021)
Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. CoRR (2021)
Patrick Plagwitz, Frank Hannig, Martin Ströbel, Christoph Strohmeyer, Jürgen Teich
A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. FCCM (2021)
Faramarz Khosravi, Alexander Raß, Jürgen Teich
Efficient Computation of Probabilistic Dominance in Multi-objective Optimization. ACM Trans. Evol. Learn. Optim. 1 (4) (2021)
Peter Brand, Joachim Falk, Jonathan Ah Sue, Johannes Brendel, Ralph Hasholzner, Jürgen Teich
Adaptive Predictive Power Management for Mobile LTE Devices. IEEE Trans. Mob. Comput. 20 (8) (2021)
Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels
. ETS (2021)
Oliver Keszöcze, Marcel Brand, Michael Witterauf, Christian Heidorn, Jürgen Teich
Aarith: an arbitrary precision number library. SAC (2021)
Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. CoRR (2021)
T. K. R. Arvind, Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. VDAT (2020)
Dominik Walter, Michael Witterauf, Jürgen Teich
Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays. MEMOCODE (2020)
Bo Qiao, M. Akif Özkan, Jürgen Teich, Frank Hannig
The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. DAC (2020)
Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende
HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. Euro-Par Workshops (2020)
Muhammad Sabih, Frank Hannig, Jürgen Teich
Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks. CoRR (2020)
Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann, Jürgen Teich
A bibliometric approach for detecting the gender gap in computer science. Commun. ACM 63 (5) (2020)
Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich
Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. HOST (2020)
Bo Qiao, Oliver Reiche, Jürgen Teich, Frank Hannig
Unveiling kernel concurrency in multiresolution filters on GPUs with an image processing DSL. GPGPU@PPoPP (2020)
Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener, Stefan Wildermann, Jürgen Teich
SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. EDBT (2020)
M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig
HipaccVX: Wedding of OpenVX and DSL-based Code Generation. CoRR (2020)
Bertrand Simon, Joachim Falk, Nicole Megow, Jürgen Teich
Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice. NG-RES@HiPEAC (2020)
Christian Heidorn, Frank Hannig, Jürgen Teich
Design space exploration for layer-parallel execution of convolutional neural networks on CGRAs. SCOPES (2020)

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Publication Activity (10 Years)

Top Topics

Top Venues

Jürgen Teich