DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks.
Jan SommerM. Akif ÖzkanOliver KeszöczeJürgen TeichPublished in: CoRR (2022)
Keyphrases
- digital signal processing
- verilog hdl
- signal processing
- systolic array
- real time image processing
- high speed
- digital signal processor
- digital signal
- data flow
- image processing
- texas instruments
- computer vision and image processing
- field programmable gate array
- digital signal processors
- real time
- low cost
- hardware implementation
- data acquisition
- case study