Oliver Keszöcze

ORCID

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 46

Top Venues

University of Bremen, Germany (PHD)

Education History

University of Bremen, Germany

PHD

Publications

Martin Lukac, Saadat Nursultan, Georgiy Krylov, Oliver Keszöcze, Abilmansur Rakhmettulayev, Michitaka Kameyama
Geometric Refactoring of Quantum and Reversible Circuits Using Graph Algorithms. IEICE Trans. Inf. Syst. 107 (8) (2024)
Matthias Kergaßner, Oliver Keszöcze, Rolf Wanka
Markov Chain-based Optimization Time Analysis of Bivalent Ant Colony Optimization for Sorting and LeadingOnes. GECCO (2024)
Matthias Kergaßner, Oliver Keszöcze, Rolf Wanka
Markov Chain-based Optimization Time Analysis of Bivalent Ant Colony Optimization for Sorting and LeadingOnes. CoRR (2024)
Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation. ARC (2024)
Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations. CoRR (2023)
Max Bartunik, Jens Kirchner, Oliver Keszöcze
Artificial intelligence for molecular communication. it Inf. Technol. 65 (4-5) (2023)
Max Bartunik, Jens Kirchner, Oliver Keszöcze
Artificial Intelligence for Molecular Communication. CoRR (2023)
Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. CoRR (2022)
Max Bartunik, Oliver Keszöcze, Benjamin Schiller, Jens Kirchner
Using Deep Learning to Demodulate Transmissions in Molecular Communication. ISMICT (2022)
Oliver Keszöcze
BDD-Based Error Metric Analysis, Computation and Optimization. IEEE Access 10 (2022)
Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. FPL (2022)
Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. it Inf. Technol. 64 (3) (2022)
Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Arved Friedemann, Oliver Keszöcze
Towards Clause Learning à la Carte through VarMonads. CoRR (2022)
Marcel Brand, Frank Hannig, Oliver Keszöcze, Jürgen Teich
Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview. IEEE Trans. Circuits Syst. II Express Briefs 69 (6) (2022)
Oliver Keszöcze
Approximate Computing. it Inf. Technol. 64 (3) (2022)
Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. CoRR (2022)
Armin Schuster, Christian Heidorn, Marcel Brand, Oliver Keszöcze, Jürgen Teich
Design Space Exploration of Time, Energy, and Error Rate Trade-offs for CNNs Using Accuracy-Programmable Instruction Set Processors. PKDD/ECML Workshops (1) (2021)
Naser Mohammadzadeh, Robert Wille, Oliver Keszöcze
Efficient One-pass Synthesis for Digital Microfluidic Biochips. ACM Trans. Design Autom. Electr. Syst. 26 (4) (2021)
Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. CoRR (2021)
Oliver Keszöcze, Marcel Brand, Michael Witterauf, Christian Heidorn, Jürgen Teich
Aarith: an arbitrary precision number library. SAC (2021)
Oliver Keszöcze, Naser Mohammadzadeh, Robert Wille
Exact Physical Design of Quantum Circuits for Ion-Trap-based Quantum Architectures. DATE (2021)
Jürgen Teich, Behnaz Pourmohseni, Oliver Keszöcze, Jan Spieck, Stefan Wildermann
Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems. ASP-DAC (2020)
Martin Lukac, Saadat Nursultan, Georgiy Krylov, Oliver Keszöcze
Geometric Refactoring of Quantum and Reversible Circuits: Quantum Layout. DSD (2020)
Andreas Wendler, Oliver Keszöcze
A fast BDD Minimization Framework for Approximate Computing. DATE (2020)
Oliver Keszöcze, Robert Wille, Rolf Drechsler
One-pass Synthesis for Digital Microfluidic Biochips: A Survey. ISDCS (2020)
Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Jürgen Teich
Probabilistic Error Propagation through Approximated Boolean Networks. DAC (2020)
Oliver Keszöcze, Ian G. Harris
Chatbot-based assertion generation from natural language specifications. FDL (2019)
Oliver Keszöcze, Mathias Soeken, Rolf Drechsler
The complexity of error metrics. Inf. Process. Lett. 139 (2018)
Oliver Keszöcze, Philipp Niemann, Arved Friedemann, Rolf Drechsler
On the complexity of design tasks for Digital Microfluidic Biochips. Microelectron. J. 78 (2018)
Wouter Castryck, Jeroen Demeyer, Alexis De Vos, Oliver Keszöcze, Mathias Soeken
Translating Between the Roots of the Identity in Quantum Computers. ISMVL (2018)
Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips. VLSI Design (2018)
Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler
Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws. ISVLSI (2018)
Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips. MBMV (2017)
Oliver Keszöcze
Exakter Entwurf digitaler mikrofluidischer Biochips. Ausgezeichnete Informatikdissertationen (2017)
Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Effects of cell shapes on the routability of Digital Microfluidic Biochips. DATE (2017)
Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Exact routing for micro-electrode-dot-array digital microfluidic biochips. ASP-DAC (2017)
Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler
BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips. ISVLSI (2017)
Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler
Synthesis of optical circuits using binary decision diagrams. Integr. 59 (2017)
Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs. J. Low Power Electron. 13 (4) (2017)
Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs - Work in Progress Report. RC (2016)
Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Generating and checking control logic in the HDL-based design of reversible circuits. ISED (2016)
Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler
Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits. ACM J. Emerg. Technol. Comput. Syst. 13 (1) (2016)
Robert Wille, Oliver Keszöcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler
Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits. ASP-DAC (2016)
Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
Embedding of Large Boolean Functions for Reversible Logic. ACM J. Emerg. Technol. Comput. Syst. 12 (4) (2016)
Robert Wille, Oliver Keszöcze, Stefan Hillmich, Marcel Walter, Alberto García Ortiz
Synthesis of approximate coders for on-chip interconnects using reversible logic. DATE (2016)
Oliver Keszöcze, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
A General and Exact Routing Methodology for Digital Microfluidic Biochips. ICCAD (2015)
Robert Wille, Oliver Keszöcze, Clemens Hopfmuller, Rolf Drechsler
Reverse BDD-based synthesis for splitter-free optical circuits. ASP-DAC (2015)
Robert Wille, Oliver Keszöcze, Rolf Drechsler, Tobias Boehnisch, Alexander Kroker
Scalable One-Pass Synthesis for Digital Microfluidic Biochips. IEEE Des. Test 32 (6) (2015)
Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler
Exact One-pass Synthesis of Digital Microfluidic Biochips. DAC (2014)
Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey
A Logic for Cardinality Constraints (Extended Abstract). MBMV (2014)
Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
Embedding of Large Boolean Functions for Reversible Logic. CoRR (2014)
Oliver Keszöcze, Robert Wille, Rolf Drechsler
Exact routing for digital microfluidic biochips with temporary blockages. ICCAD (2014)
Dave W. Binkley, Dawn J. Lawrie, Emily Hill, Janet E. Burge, Ian G. Harris, Regina Hebig, Oliver Keszöcze, Karl Reed, John Slankas
Task-Driven Software Summarization. ICSM (2013)
Robert Wille, Oliver Keszöcze, Rolf Drechsler
Determining the minimal number of lines for large reversible circuits. DATE (2011)

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Publication Activity (10 Years)

Top Topics

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Oliver Keszöcze