Michael Witterauf

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 16

Top Topics

Parallel Architectures

Top Venues

ACM Trans. Embed. Comput. Syst.

Publications

Dominik Walter, Marcel Brand, Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich
ALPACA: An Accelerator Chip for Nested Loop Programs. ISCAS (2024)
Marcel Brand, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. 33 (14) (2021)
Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. ACM Trans. Embed. Comput. Syst. 20 (5) (2021)
Oliver Keszöcze, Marcel Brand, Michael Witterauf, Christian Heidorn, Jürgen Teich
Aarith: an arbitrary precision number library. SAC (2021)
Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. CoRR (2021)
Dominik Walter, Michael Witterauf, Jürgen Teich
Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays. MEMOCODE (2020)
Marcel Brand, Michael Witterauf, Alberto Bosio, Jürgen Teich
Anytime Floating-Point Addition and Multiplication-Concepts and Implementations. ASAP (2020)
Marcel Brand, Michael Witterauf, Frank Hannig, Jürgen Teich
Anytime instructions for programmable accuracy floating-point arithmetic. CF (2019)
Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich
Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. J. Comput. 14 (8) (2019)
Michael Witterauf, Frank Hannig, Jürgen Teich
Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays. MEMOCODE (2019)
Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich
Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. ASAP (2018)
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Trans. Embed. Comput. Syst. 17 (2) (2018)
Michael Witterauf, Jürgen Teich
Run-time Requirement Enforcement for Loop Programs on Processor Arrays. MEMOCODE (2018)
Michael Witterauf, Frank Hannig, Jürgen Teich
Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. RSP (2017)
Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich
Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. ASAP (2016)
Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker
Providing fault tolerance through invasive computing. it Inf. Technol. 58 (6) (2016)
Michael Witterauf, Alexandru Tanase, Jürgen Teich, Vahid Lari, Andreas Zwinkau, Gregor Snelting
Adaptive fault tolerance through invasive computing. AHS (2015)
Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer
Techniques for on-demand structural redundancy for massively parallel processor arrays. J. Syst. Archit. 61 (10) (2015)
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari
On-demand fault-tolerant loop processing on massively parallel processor arrays. ASAP (2015)
Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS (2015)
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. MEMOCODE (2015)
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
Symbolic inner loop parallelisation for massively parallel processor arrays. MEMOCODE (2014)