Brett H. Meyer

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 56

Top Topics

Semantic Segmentation

Application Specific

Fault Injection

Top Venues

ACM Great Lakes Symposium on VLSI

Publications

Lulan Shen, Ali Edalati, Brett H. Meyer, Warren J. Gross, James J. Clark
AdCorDA: Classifier Refinement via Adversarial Correction and Domain Adaptation. CoRR (2024)
Lulan Shen, Ali Edalati, Brett H. Meyer, Warren J. Gross, James J. Clark
Robustness to distribution shifts of compressed networks for edge devices. CoRR (2024)
Mohammadreza Tayaranian, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross
Faster Inference of Integer SWIN Transformer by Removing the GELU Activation. CoRR (2024)
Mohammadreza Tayaranian, Seyyed Hasan Mozafari, Brett H. Meyer, James J. Clark, Warren J. Gross
Automatic Pruning of Fine-tuning Datasets for Transformer-based Language Models. CoRR (2024)
Zhuoran Xiong, Marihan Amein, Olivier Therrien, Warren J. Gross, Brett H. Meyer
FMAS: Fast Multi-Objective SuperNet Architecture Search for Semantic Segmentation. CoRR (2023)
Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer
Training Acceleration of Frequency Domain CNNs Using Activation Compression. ISCAS (2023)
Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer
Efficient 1D Grouped Convolution for PyTorch a Case Study: Fast On-Device Fine-Tuning for SqueezeBERT. ASAP (2023)
Olivier Therrien, Marihan Amein, Zhuoran Xiong, Warren J. Gross, Brett H. Meyer
SSS3D: Fast Neural Architecture Search For Efficient Three-Dimensional Semantic Segmentation. CoRR (2023)
Hung-Yang Chang, Seyyed Hasan Mozafari, Cheng Chen, James J. Clark, Brett H. Meyer, Warren J. Gross
PipeBERT: High-throughput BERT Inference for ARM Big.LITTLE Multi-core Processors. J. Signal Process. Syst. 95 (7) (2023)
Jarul Mehta, Guillaume Richard, Loren Lugosch, Derek Yu, Brett H. Meyer
DT-DS: CAN Intrusion Detection with Decision Tree Ensembles. ACM Trans. Cyber Phys. Syst. 7 (1) (2023)
Hung-Yang Chang, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross
High-Throughput Edge Inference for BERT Models via Neural Architecture Search and Pipeline. ACM Great Lakes Symposium on VLSI (2023)
Lulan Shen, Ibtihel Amara, Ruofeng Li, Brett H. Meyer, Warren J. Gross, James J. Clark
Fast Fine-Tuning Using Curriculum Domain Adaptation. CRV (2023)
Amir Ardakani, Arash Ardakani, Brett H. Meyer, James J. Clark, Warren J. Gross
Standard Deviation-Based Quantization for Deep Neural Networks. CoRR (2022)
Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross
Efficient Fine-Tuning of BERT Models on the Edge. CoRR (2022)
Ibtihel Amara, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark
CES-KD: Curriculum-based Expert Selection for Guided Knowledge Distillation. ICPR (2022)
Negin Firouzian, Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer
Work-in-Progress: Utilizing latency and accuracy predictors for efficient hardware-aware NAS. CODES+ISSS (2022)
Murray L. Kornelsen, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross
Fast Heterogeneous Task Mapping for Reducing Edge DNN Latency. ASAP (2022)
Lulan Shen, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark
Conjugate Adder Net (CAddNet) - a Space-Efficient Approximate CNN. CVPR Workshops (2022)
Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross
Efficient Fine-Tuning of BERT Models on the Edge. ISCAS (2022)
M. Abdelgawad, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross
BERTPerf: Inference Latency Predictor for BERT on ARM big.LITTLE Multi-Core Processors. SiPS (2022)
Ibtihel Amara, Nazanin Mohammadi Sepahvand, Brett H. Meyer, Warren J. Gross, James J. Clark
BD-KD: Balancing the Divergences for Online Knowledge Distillation. CoRR (2022)
Marihan Amein, Zhuoran Xiong, Olivier Therrien, Brett H. Meyer, Warren J. Gross
Work-in-Progress: SuperNAS: Fast Multi-Objective SuperNet Architecture Search for Semantic Segmentation. CASES (2022)
Ibtihel Amara, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark
CES-KD: Curriculum-based Expert Selection for Guided Knowledge Distillation. CoRR (2022)
Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross
Efficient Fine-Tuning of Compressed Language Models with Learners. CoRR (2022)
Warren J. Gross, Brett H. Meyer, Arash Ardakani
Hardware-Aware Design for Edge Intelligence. IEEE Open J. Circuits Syst. 2 (2021)
Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer
Implementing Convolutional Neural Networks Using Hartley Stochastic Computing With Adaptive Rate Feature Map Compression. IEEE Open J. Circuits Syst. 2 (2021)
Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer
Hartley Stochastic Computing For Convolutional Neural Networks. SiPS (2021)
Márton Búr, Kristóf Marussy, Brett H. Meyer, Dániel Varró
Worst-case Execution Time Calculation for Query-based Monitors by Witness Generation. ACM Trans. Embed. Comput. Syst. 20 (6) (2021)
Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
A Design Framework for Invertible Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (4) (2021)
Márton Búr, Kristóf Marussy, Brett H. Meyer, Dániel Varró
Worst-Case Execution Time Calculation for Query-Based Monitors by Witness Generation. CoRR (2021)
Zixuan Yin, Warren J. Gross, Brett H. Meyer
Probabilistic Sequential Multi-Objective Optimization of Convolutional Neural Networks. DATE (2020)
Naoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (5) (2020)
Loren Lugosch, Brett H. Meyer, Derek Nowrouzezahrai, Mirco Ravanelli
Using Speech Synthesis to Train End-To-End Spoken Language Understanding Models. ICASSP (2020)
Seyyed Hasan Mozafari, Brett H. Meyer
Hot sparing for lifetime-chip-performance and cost improvement in application specific SIMT processors. Des. Autom. Embed. Syst. 24 (4) (2020)
Loren Lugosch, Derek Nowrouzezahrai, Brett H. Meyer
Surprisal-Triggered Conditional Computation with Neural Networks. CoRR (2020)
Zaid Al-bayati, Youcheng Sun, Haibo Zeng, Marco Di Natale, Qi Zhu, Brett H. Meyer
Partitioning and Selection of Data Consistency Mechanisms for Multicore Real-Time Systems. ACM Trans. Embed. Comput. Syst. 18 (4) (2019)
Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
Efficient CMOS Invertible Logic Using Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2019)
Seyyed Hasan Mozafari, Brett H. Meyer
Characterizing the Effectiveness of Hot Sparing on Cost and Performance-per-Watt in Application Specific SIMT. Integr. 69 (2019)
Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
A Design Framework for Invertible Logic. ACSSC (2019)
Arash Ardakani, Zhengyun Ji, Sean C. Smithson, Brett H. Meyer, Warren J. Gross
Learning Recurrent Binary/Ternary Weights. ICLR (Poster) (2019)
Derek Yu, Michael Vaquier, Evan Laflamme, Gabrielle Doucette-Poirier, Justin Tremblay, Brett H. Meyer
ARINC-825TBv2: A Hardware-in-the-Ioop Simulation Platform for Aerospace Security Research. RSP (2019)
Jonah Caplan, Zaid Al-bayati, Haibo Zeng, Brett H. Meyer
Mapping and Scheduling Mixed-Criticality Systems with On-Demand Redundancy. IEEE Trans. Computers 67 (4) (2018)
Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
Study of Stochastic Invertible Multiplier Designs. ICECS (2018)
Seyyed Hasan Mozafari, Brett H. Meyer
Efficient Performance Evaluation of Multi-Core SIMT Processors with Hot Redundancy. IEEE Trans. Emerg. Top. Comput. 6 (4) (2018)
Arash Ardakani, Zhengyun Ji, Sean C. Smithson, Brett H. Meyer, Warren J. Gross
Learning Recurrent Binary/Ternary Weights. CoRR (2018)
Calvin Ma, Aditya Mahajan, Brett H. Meyer
Multi-armed bandits for efficient lifetime estimation in MPSoC design. DATE (2017)
Maria Isabel Mera, Jonah Caplan, Seyyed Hasan Mozafari, Brett H. Meyer, Peter A. Milder
Area, Throughput, and Power Trade-Offs for FPGA- and ASIC-Based Execution Stream Compression. ACM Trans. Embed. Comput. Syst. 16 (4) (2017)
Zaid Al-bayati, Jonah Caplan, Brett H. Meyer, Haibo Zeng
A four-mode model for efficient fault-tolerant mixed-criticality systems. DATE (2016)
Sean C. Smithson, Guang Yang, Warren J. Gross, Brett H. Meyer
Neural Networks Designing Neural Networks: Multi-Objective Hyper-Parameter Optimization. CoRR (2016)
Dimitrios Stamoulis, Simone Corbetta, Dimitrios Rodopoulos, Pieter Weckx, Peter Debacker, Brett H. Meyer, Ben Kaczer, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic
Capturing True Workload Dependency of BTI-induced Degradation in CPU Components. ACM Great Lakes Symposium on VLSI (2016)
Zaid Al-bayati, Brett H. Meyer, Haibo Zeng
Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures. DFT (2016)
Mojing Liu, Brett H. Meyer
Bounding error detection latency in safety critical systems with enhanced Execution Fingerprinting. DFT (2016)
Sean C. Smithson, Kaushik Boga, Arash Ardakani, Brett H. Meyer, Warren J. Gross
Stochastic Computing Can Improve Upon Digital Spiking Neural Networks. SiPS (2016)
Sean C. Smithson, Guang Yang, Warren J. Gross, Brett H. Meyer
Neural networks designing neural networks: multi-objective hyper-parameter optimization. ICCAD (2016)
Runjie Zhang, Brett H. Meyer, Ke Wang, Mircea R. Stan, Kevin Skadron
Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Scott Dickson Dagondon, Warren J. Gross, Brett H. Meyer
Sparse-Clustered Network with Selective Decoding for Internet Traffic Classification. SiPS (2016)
Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron, Mircea R. Stan
Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC. ISLPED (2015)
Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer
Techniques for on-demand structural redundancy for massively parallel processor arrays. J. Syst. Archit. 61 (10) (2015)
Seyyed Hasan Mozafari, Brett H. Meyer
Hot spare components for performance-cost improvement in multi-core SIMT. DFTS (2015)
Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic
Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models. ACM Great Lakes Symposium on VLSI (2015)
Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron, Mircea R. Stan
A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC. DAC (2015)
Seyyed Hasan Mozafari, Brett H. Meyer, Kevin Skadron
Yield-aware Performance-Cost Characterization for Multi-Core SIMT. ACM Great Lakes Symposium on VLSI (2015)
Badrun Nahar, Brett H. Meyer
RotR: Rotational redundant task mapping for fail-operational MPSoCs. DFTS (2015)
Zaid Al-bayati, Youcheng Sun, Haibo Zeng, Marco Di Natale, Qi Zhu, Brett H. Meyer
Task placement and selection of data consistency mechanisms for real-time multicore applications. RTAS (2015)
Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS (2015)
Brett H. Meyer, Adam S. Hartman, Donald E. Thomas
Cost-effective lifetime and yield optimization for NoC-based MPSoCs. ACM Trans. Design Autom. Electr. Syst. 19 (2) (2014)
Saad Arrabi, D. Moore, L. Wang, Kevin Skadron, Benton H. Calhoun, John C. Lach, Brett H. Meyer
Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems. FCCM (2014)
Ke Wang, Brett H. Meyer, Runjie Zhang, Kevin Skadron, Mircea R. Stan
Walking pads: Fast power-supply pad-placement optimization. ASP-DAC (2014)
Jonah Caplan, Maria Isabel Mera, Peter A. Milder, Brett H. Meyer
Trade-offs in execution signature compression for reliable processor systems. DATE (2014)
Ke Wang, Brett H. Meyer, Runjie Zhang, Mircea R. Stan, Kevin Skadron
Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization. DAC (2014)
Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Zeljko Zilic
Linear regression techniques for efficient analysis of transistor variability. ICECS (2014)
Chen Jiang, Mojing Liu, Brett H. Meyer
MB-FICA: multi-bit fault injection and coverage analysis. ACM Great Lakes Symposium on VLSI (2014)
Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan, Kevin Skadron
Architecture implications of pads as a scarce resource. ISCA (2014)
Karthik Sankaranarayanan, Brett H. Meyer, Wei Huang, Robert J. Ribando, Hossein Haj-Hariri, Mircea R. Stan, Kevin Skadron
Architectural implications of spatial thermal filtering. Integr. 46 (1) (2013)
Lukasz G. Szafaryn, Brett H. Meyer, Kevin Skadron
Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core. IEEE Micro 33 (4) (2013)
Gregory G. Faust, Runjie Zhang, Kevin Skadron, Mircea R. Stan, Brett H. Meyer
ArchFP: Rapid prototyping of pre-RTL floorplans. VLSI-SoC (2012)
Brett H. Meyer, Nishant J. George, Benton H. Calhoun, John C. Lach, Kevin Skadron
Reducing the cost of redundant execution in safety-critical systems using relaxed dedication. DATE (2011)
Karthik Sankaranarayanan, Brett H. Meyer, Mircea R. Stan, Kevin Skadron
Thermal benefit of multi-core floorplanning: A limits study. Sustain. Comput. Informatics Syst. 1 (4) (2011)
Brett H. Meyer, Benton H. Calhoun, John C. Lach, Kevin Skadron
Cost-effective safety and fault localization using distributed temporal redundancy. CASES (2011)
Brett H. Meyer, Adam S. Hartman, Donald E. Thomas
Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs. DATE (2010)
Brett H. Meyer, Adam S. Hartman, Donald E. Thomas
Slack allocation for yield improvement in NoC-based MPSoCs. ISQED (2010)
Adam S. Hartman, Donald E. Thomas, Brett H. Meyer
A case for lifetime-aware task mapping in embedded chip multiprocessors. CODES+ISSS (2010)
Zhenyu Qi, Brett H. Meyer, Wei Huang, Robert J. Ribando, Kevin Skadron, Mircea R. Stan
Temperature-to-power mapping. ICCD (2010)
Brett H. Meyer, Donald E. Thomas
Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoC. Des. Autom. Embed. Syst. 13 (1-2) (2009)
Brett H. Meyer, Donald E. Thomas
Rethinking Automated Synthesis of MPSoC Architectures. IPDPS (2007)
Brett H. Meyer, Donald E. Thomas
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC. CODES+ISSS (2007)
JoAnn M. Paul, Brett H. Meyer
Amdahl's Law Revisited for Single Chip Systems. Int. J. Parallel Program. 35 (2) (2007)
Brett H. Meyer, Joshua J. Pieper, JoAnn M. Paul, Jeffrey E. Nelson, Sean M. Pieper, Anthony G. Rowe
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors. IEEE Trans. Computers 54 (6) (2005)