In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning.
Naoya OnizawaSean C. SmithsonBrett H. MeyerWarren J. GrossTakahiro HanyuPublished in: IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (2020)
Keyphrases
- chip design
- machine learning
- low cost
- circuit design
- single chip
- digital circuits
- high speed
- image sensor
- random access memory
- analog vlsi
- low power
- design methodology
- supervised learning
- vlsi implementation
- cmos image sensor
- physical design
- programmable logic
- mixed signal
- real time
- power dissipation
- learning algorithm
- decision trees
- delay insensitive
- training set
- hardware and software
- power consumption
- low power consumption
- host computer
- ibm zenterprise
- signal processor
- field effect transistors
- evolvable hardware
- memory access
- multithreading
- feature selection
- design considerations
- dynamic range
- text classification
- knowledge representation