Takahiro Hanyu

ORCID

Publication Activity (10 Years)

Years Active: 1987-2024
Publications (10 Years): 80

Top Venues

ISMVL

IEICE Trans. Inf. Syst.

NEWCAS

ICECS

Publications

Ken Asano, Masanori Natsui, Takahiro Hanyu
Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network Hardware. IEICE Trans. Inf. Syst. 107 (8) (2024)
Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems. IEEE Access 12 (2024)
Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems. CoRR (2023)
Ken Asano, Masanori Natsui, Takahiro Hanyu
Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network. ICECS (2023)
Naoya Onizawa, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu
Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic. IEEE Access 11 (2023)
Kaede Sakai, Masanori Natsui, Takahiro Hanyu
Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing. MWSCAS (2023)
Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
Improving Stochastic Quantum-Like Annealing Based on Rerandomization. ICECS (2023)
Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu
Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing. CoRR (2023)
Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
Stochastic Implementation of Simulated Quantum Annealing on PYNQ. ICFPT (2023)
Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing. IEEE Trans. Neural Networks Learn. Syst. 34 (12) (2023)
Fangcen Zhong, Masanori Natsui, Takahiro Hanyu
High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control. ISCAS (2023)
Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (1) (2023)
Ken Asano, Masanori Natsui, Takahiro Hanyu
Write-Energy Relaxation of MTJ-Based Quantized Neural-Network Hardware. ISMVL (2023)
Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN. FLAP 9 (3) (2022)
Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing. ICECS 2022 (2022)
Keisuke Sakamoto, Masanori Natsui, Takahiro Hanyu
Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator. MWSCAS (2022)
Daisuke Suzuki, Takahiro Hanyu
A Spintronics-Based Nonvolatile FPGA and Its Application to Edge-AI Accelerator. MCSoC (2022)
Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu
Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices. IEEE Open J. Circuits Syst. 2 (2021)
Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu
Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (1) (2021)
Daisuke Suzuki, Takahiro Hanyu
Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow. IEICE Trans. Inf. Syst. (8) (2021)
Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu
Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices. SiPS (2021)
Naoya Onizawa, Makoto Kato, Hitoshi Yamagata, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu
Sparse Random Signals for Fast Convergence on Invertible Logic. IEEE Access 9 (2021)
Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. IEEE J. Solid State Circuits 56 (4) (2021)
Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
A Design Framework for Invertible Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (4) (2021)
Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu
A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once- Write Shifting. MCSoC (2021)
Naoya Onizawa, Takahiro Hanyu
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians. ISCAS (2021)
Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic. IEEE Access 8 (2020)
Naoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (5) (2020)
Daisuke Suzuki, Takahiro Hanyu
Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA. ISMVL (2020)
Naoya Onizawa, Duckgyu Shin, Takahiro Hanyu
Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic. FLAP 7 (1) (2020)
Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter. IEEE Trans. Very Large Scale Integr. Syst. 28 (10) (2020)
Akira Tamakoshi, Naoya Onizawa, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices. NEWCAS (2020)
Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu
Memristive Computational Memory Using Memristor Overwrite Logic (MOL). IEEE Trans. Very Large Scale Integr. Syst. 28 (11) (2020)
Makoto Kato, Naoya Onizawa, Takahiro Hanyu
Design Automation of Invertible Logic Circuit from a Standard HDL Description. FLAP 8 (5) (2020)
Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. VLSI Circuits (2020)
Naoya Onizawa, Ren Arakawa, Takahiro Hanyu
Design of an MTJ-based Nonvolatile Multi-context Ternary Content-addressable Memory. FLAP 7 (1) (2020)
Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
Efficient CMOS Invertible Logic Using Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2019)
Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic. ICECS (2019)
Tomoki Chiba, Masanori Natsui, Takahiro Hanyu
Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks. ISMVL (2019)
Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
A Design Framework for Invertible Logic. ACSSC (2019)
Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
Stochastic-Computing Based Brainwave LSI Towards an Intelligence Edge. ICECS (2019)
Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu
Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices. Microelectron. J. 83 (2019)
Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu
Multi-Context TCAM Based Selective Computing Architecture for a Low-Power NN. ICECS (2019)
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. ISSCC (2019)
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. IEEE J. Solid State Circuits 54 (11) (2019)
Daisuke Suzuki, Takahiro Hanyu
Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only). FPGA (2018)
Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
Study of Stochastic Invertible Multiplier Designs. ICECS (2018)
Kaushik Boga, François Leduc-Primeau, Naoya Onizawa, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross
A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception. J. Signal Process. Syst. 90 (5) (2018)
Jean-Philippe Diguet, Naoya Onizawa, Mostafa Rizk, Martha Johanna Sepúlveda, Amer Baghdadi, Takahiro Hanyu
Networked Power-Gated MRAMs for Memory-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. 26 (12) (2018)
Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
MTJ-based asynchronous circuits for Re-initialization free computing against power failures. Microelectron. J. 82 (2018)
Hiroki Suda, Masanori Natsui, Takahiro Hanyu
Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction. ISMVL (2018)
Shogo Mukaida, Naoya Onizawa, Takahiro Hanyu
Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter. ISMVL (2018)
Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata
High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure. ISCAS (2018)
Masanori Natsui, Tomoki Chiba, Takahiro Hanyu
Design of MTJ-Based nonvolatile logic gates for quantized neural networks. Microelectron. J. 82 (2018)
Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage-Frequency-Length Scaling. IEEE J. Emerg. Sel. Topics Circuits Syst. 8 (3) (2018)
Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu
Design of stochastic asymmetric compensation filters for auditory signal processing. GlobalSIP (2017)
Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu
Evaluation of Stochastic Cascaded IIR Filters. ISMVL (2017)
Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. DATE (2017)
Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu
Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors. IEEE Trans. Emerg. Top. Comput. 5 (2) (2017)
Mostafa Rizk, Jean-Philippe Diguet, Naoya Onizawa, Amer Baghdadi, Martha Johanna Sepúlveda, Y. Akgul, Vincent Gripon, Takahiro Hanyu
NoC-MRAM architecture for memory-based computing: Database-search case study. NEWCAS (2017)
Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda
MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. ASYNC (2017)
Daisuke Suzuki, Takahiro Hanyu
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme. IEICE Trans. Inf. Syst. (8) (2017)
Takahiro Hanyu
Foreword. IEICE Trans. Inf. Syst. (8) (2017)
Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. IEEE Trans. Very Large Scale Integr. Syst. 25 (10) (2017)
Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu
Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation. IEEE Trans. Very Large Scale Integr. Syst. 25 (10) (2017)
Naoya Onizawa, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability. ESSCIRC (2017)
Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata
High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation. IEICE Trans. Inf. Syst. (8) (2017)
Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno
An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (2) (2016)
Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu
Gammatone filter based on stochastic computation. ICASSP (2016)
Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory. J. Multiple Valued Log. Soft Comput. 26 (1-2) (2016)
Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross
Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (1) (2016)
Naoto Sugaya, Masanori Natsui, Takahiro Hanyu
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission. ISMVL (2016)
Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata
Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation. ISMVL (2016)
Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
VLSI implementation of deep neural networks using integral stochastic computing. ISTC (2016)
Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE 104 (10) (2016)
Daisuke Suzuki, Takahiro Hanyu
A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure. FPL (2016)
Daisuke Suzuki, Takahiro Hanyu
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme. ISMVL (2016)
Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS (2016)
Naoya Onizawa, Takahiro Hanyu
Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations. NEWCAS (2016)
Masanori Natsui, Naoto Sugaya, Takahiro Hanyu
A study of a top-down error correction technique using Recurrent-Neural-Network-based learning. NEWCAS (2016)
Kaushik Boga, Naoya Onizawa, François Leduc-Primeau, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross
Stochastic implementation of the disparity energy model for depth perception. SiPS (2015)
Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
Frequency-flexible stochastic Gabor filter. DSP (2015)
Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery. NANOARCH (2015)
Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
Gabor Filter Based on Stochastic Computation. IEEE Signal Process. Lett. 22 (9) (2015)
Akira Mochizuki, Naoto Yube, Takahiro Hanyu
Design of a computational nonvolatile RAM for a greedy energy-efficient VLSI processor. IECON (2015)
Naoya Onizawa, Shunsuke Koshita, Takahiro Hanyu
Scaled IIR filter based on stochastic computation. MWSCAS (2015)
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. VLSIC (2015)
Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. DATE (2015)
Satoshi Oosawa, Takayuki Konishi, Naoya Onizawa, Takahiro Hanyu
Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop. NEWCAS (2015)
Takeaki Akutsu, Masanori Natsui, Takahiro Hanyu
Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. ISMVL (2015)
Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. CoRR (2015)
Daisuke Suzuki, Takahiro Hanyu
Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure. MWSCAS (2015)
Daisaku Katagiri, Naoya Onizawa, Takahiro Hanyu
Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors. ISMVL (2015)
Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits 50 (2) (2015)
Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu
Analog-to-stochastic converter using magnetic-tunnel junction devices. NANOARCH (2014)
Akira Mochizuki, Hirokatsu Shirahama, Yuma Watanabe, Takahiro Hanyu
Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip. IEICE Trans. Inf. Syst. (9) (2014)
Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
Associative Memories Based on Multiple-Valued Sparse Clustered Networks. ISMVL (2014)
Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express 11 (10) (2014)
Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu
A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure. ASYNC (2014)
Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2014)

Takahiro Hanyu.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Takahiro Hanyu