Duckgyu Shin

Publication Activity (10 Years)

Years Active: 2019-2024
Publications (10 Years): 12

Top Topics

Combinatorial Optimization

Fpga Implementation

Simulated Annealing

Top Venues

Publications

Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems. IEEE Access 12 (2024)
Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems. CoRR (2023)
Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
Improving Stochastic Quantum-Like Annealing Based on Rerandomization. ICECS (2023)
Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu
Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing. CoRR (2023)
Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
Stochastic Implementation of Simulated Quantum Annealing on PYNQ. ICFPT (2023)
Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing. IEEE Trans. Neural Networks Learn. Syst. 34 (12) (2023)
Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (1) (2023)
Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN. FLAP 9 (3) (2022)
Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing. ICECS 2022 (2022)
Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic. IEEE Access 8 (2020)
Naoya Onizawa, Duckgyu Shin, Takahiro Hanyu
Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic. FLAP 7 (1) (2020)
Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic. ICECS (2019)