FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic.

Duckgyu Shin Naoya Onizawa Takahiro Hanyu

Published in: ICECS (2019)

Keyphrases

fpga implementation
perceptron learning
hardware implementation
field programmable gate array
delay insensitive
chip design
low cost
random access memory

asynchronous circuits
efficient implementation
digital circuits
circuit design
high speed
power consumption
input image

radial basis function
single chip
image processing algorithms
neural network
parallel computing
generalization error
low power

signal processing
image processing
real time
embedded systems
image sensor
machine learning
pattern recognition