Naoya Onizawa

ORCID

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 53

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

ISMVL

NEWCAS

ICECS

Publications

Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems. IEEE Access 12 (2024)
Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems. CoRR (2023)
Naoya Onizawa, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu
Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic. IEEE Access 11 (2023)
Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
Improving Stochastic Quantum-Like Annealing Based on Rerandomization. ICECS (2023)
Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu
Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing. CoRR (2023)
Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
Stochastic Implementation of Simulated Quantum Annealing on PYNQ. ICFPT (2023)
Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing. IEEE Trans. Neural Networks Learn. Syst. 34 (12) (2023)
Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (1) (2023)
Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN. FLAP 9 (3) (2022)
Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing. ICECS 2022 (2022)
Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu
Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices. IEEE Open J. Circuits Syst. 2 (2021)
Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu
Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (1) (2021)
Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu
Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices. SiPS (2021)
Naoya Onizawa, Makoto Kato, Hitoshi Yamagata, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu
Sparse Random Signals for Fast Convergence on Invertible Logic. IEEE Access 9 (2021)
Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
A Design Framework for Invertible Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (4) (2021)
Naoya Onizawa, Takahiro Hanyu
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians. ISCAS (2021)
Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic. IEEE Access 8 (2020)
Naoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (5) (2020)
Naoya Onizawa, Duckgyu Shin, Takahiro Hanyu
Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic. FLAP 7 (1) (2020)
Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter. IEEE Trans. Very Large Scale Integr. Syst. 28 (10) (2020)
Akira Tamakoshi, Naoya Onizawa, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices. NEWCAS (2020)
Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu
Memristive Computational Memory Using Memristor Overwrite Logic (MOL). IEEE Trans. Very Large Scale Integr. Syst. 28 (11) (2020)
Makoto Kato, Naoya Onizawa, Takahiro Hanyu
Design Automation of Invertible Logic Circuit from a Standard HDL Description. FLAP 8 (5) (2020)
Naoya Onizawa, Ren Arakawa, Takahiro Hanyu
Design of an MTJ-based Nonvolatile Multi-context Ternary Content-addressable Memory. FLAP 7 (1) (2020)
Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
Efficient CMOS Invertible Logic Using Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2019)
Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic. ICECS (2019)
Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
A Design Framework for Invertible Logic. ACSSC (2019)
Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
Stochastic-Computing Based Brainwave LSI Towards an Intelligence Edge. ICECS (2019)
Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu
Multi-Context TCAM Based Selective Computing Architecture for a Low-Power NN. ICECS (2019)
Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
Study of Stochastic Invertible Multiplier Designs. ICECS (2018)
Kaushik Boga, François Leduc-Primeau, Naoya Onizawa, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross
A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception. J. Signal Process. Syst. 90 (5) (2018)
Jean-Philippe Diguet, Naoya Onizawa, Mostafa Rizk, Martha Johanna Sepúlveda, Amer Baghdadi, Takahiro Hanyu
Networked Power-Gated MRAMs for Memory-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. 26 (12) (2018)
Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
MTJ-based asynchronous circuits for Re-initialization free computing against power failures. Microelectron. J. 82 (2018)
Shogo Mukaida, Naoya Onizawa, Takahiro Hanyu
Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter. ISMVL (2018)
Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata
High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure. ISCAS (2018)
Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage-Frequency-Length Scaling. IEEE J. Emerg. Sel. Topics Circuits Syst. 8 (3) (2018)
Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu
Design of stochastic asymmetric compensation filters for auditory signal processing. GlobalSIP (2017)
Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu
Evaluation of Stochastic Cascaded IIR Filters. ISMVL (2017)
Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. DATE (2017)
Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu
Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors. IEEE Trans. Emerg. Top. Comput. 5 (2) (2017)
Mostafa Rizk, Jean-Philippe Diguet, Naoya Onizawa, Amer Baghdadi, Martha Johanna Sepúlveda, Y. Akgul, Vincent Gripon, Takahiro Hanyu
NoC-MRAM architecture for memory-based computing: Database-search case study. NEWCAS (2017)
Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda
MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. ASYNC (2017)
Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. IEEE Trans. Very Large Scale Integr. Syst. 25 (10) (2017)
Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu
Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation. IEEE Trans. Very Large Scale Integr. Syst. 25 (10) (2017)
Naoya Onizawa, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability. ESSCIRC (2017)
Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata
High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation. IEICE Trans. Inf. Syst. (8) (2017)
Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu
Gammatone filter based on stochastic computation. ICASSP (2016)
Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory. J. Multiple Valued Log. Soft Comput. 26 (1-2) (2016)
Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross
Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (1) (2016)
Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata
Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation. ISMVL (2016)
Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
VLSI implementation of deep neural networks using integral stochastic computing. ISTC (2016)
Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE 104 (10) (2016)
Naoya Onizawa, Takahiro Hanyu
Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations. NEWCAS (2016)
Kaushik Boga, Naoya Onizawa, François Leduc-Primeau, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross
Stochastic implementation of the disparity energy model for depth perception. SiPS (2015)
Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
Frequency-flexible stochastic Gabor filter. DSP (2015)
Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery. NANOARCH (2015)
Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
Gabor Filter Based on Stochastic Computation. IEEE Signal Process. Lett. 22 (9) (2015)
Naoya Onizawa, Shunsuke Koshita, Takahiro Hanyu
Scaled IIR filter based on stochastic computation. MWSCAS (2015)
Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. DATE (2015)
Satoshi Oosawa, Takayuki Konishi, Naoya Onizawa, Takahiro Hanyu
Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop. NEWCAS (2015)
Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. CoRR (2015)
Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross
Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks. IEEE Trans. Very Large Scale Integr. Syst. 23 (4) (2015)
Daisaku Katagiri, Naoya Onizawa, Takahiro Hanyu
Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors. ISMVL (2015)
Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu
Analog-to-stochastic converter using magnetic-tunnel junction devices. NANOARCH (2014)
Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
Associative Memories Based on Multiple-Valued Sparse Clustered Networks. ISMVL (2014)
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross
Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks. J. Signal Process. Syst. 76 (3) (2014)
Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu
A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure. ASYNC (2014)
Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2014)
Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. (6) (2014)
Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
Associative Memories Based on Multiple-Valued Sparse Clustered Networks. CoRR (2014)
Naoya Onizawa, Takahiro Hanyu
Soft-error tolerant transistor/magnetic-tunnel-junction hybrid non-volatile C-element. IEICE Electron. Express 11 (24) (2014)
Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu
High-Throughput Compact Delay-Insensitive Asynchronous NoC Router. IEEE Trans. Computers 63 (3) (2014)
Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model. IEICE Trans. Inf. Syst. (9) (2014)
Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link. APCCAS (2014)
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. 4 (4) (2014)
Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
Soft-Delay-Error Evaluation in Content-Addressable Memory. ISMVL (2014)
Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model. J. Signal Process. Syst. 76 (2) (2014)
Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu
Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM. NEWCAS (2014)
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Takahiro Hanyu, Warren J. Gross
Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories. SiPS (2014)
Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating. ISMVL (2013)
Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu
High-throughput CAM based on a synchronous overlapped search scheme. IEICE Electron. Express 10 (7) (2013)
Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems. ASYNC (2013)
Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links. IEICE Trans. Inf. Syst. (9) (2013)
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross
Reduced-complexity binary-weight-coded associative memories. ICASSP (2013)
Hooman Jarollahi, Naoya Onizawa, Warren J. Gross
Selective Decoding in Associative Memories Based on Sparse-Clustered Networks. CoRR (2013)
Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross
A low-power Content-Addressable Memory based on clustered-sparse networks. ASAP (2013)
Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross
A Low-Power Content-Addressable-Memory Based on Clustered-Sparse-Networks CoRR (2013)
Hooman Jarollahi, Naoya Onizawa, Warren J. Gross
Selective decoding in associative memories based on Sparse-Clustered Networks. GlobalSIP (2013)
Naoya Onizawa, Warren J. Gross
Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks. DAC (2013)
Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
Clockless Stochastic Decoding of Low-Density Parity-Check Codes. SiPS (2012)
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross
Architecture and implementation of an associative memory using sparse clustered networks. ISCAS (2012)
Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
Multi-chip NoCs for Automotive Applications. PRDC (2012)
Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2012)
Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism. ASYNC (2012)
Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu, Warren J. Gross
Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes. ISMVL (2012)
Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu
Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links. ISMVL (2012)
Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system. ISCAS (2011)
Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu
Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links. ISMVL (2011)
Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu
Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2011)
Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring. DATE (2011)

Naoya Onizawa.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Naoya Onizawa