Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices.
Naoya OnizawaAkira TamakoshiTakahiro HanyuPublished in: SiPS (2021)
Keyphrases
- hardware architecture
- coefficient matrix
- sparse matrix
- hardware implementation
- hardware architectures
- modal logic
- associative memory
- binary matrices
- low rank matrix
- high dimensional
- processing elements
- field programmable gate array
- block matching motion estimation
- low rank approximation
- singular value decomposition
- low rank
- neural network model
- rows and columns
- fine grained
- software engineering
- pattern recognition
- image processing
- feature selection
- neural network