Hiroki Koike

Publication Activity (10 Years)

Years Active: 1990-2022
Publications (10 Years): 10

Top Topics

Energy Dissipation

Integrated Circuit

Positional Information

Top Venues

Des. Codes Cryptogr.

IEEE J. Emerg. Sel. Topics Circuits Syst.

Publications

K. Watanabe, T. Shimada, K. Hirose, H. Shindo, D. Kobayashi, Takaho Tanigawa, Shoji Ikeda, Takamitsu Shinada, Hiroki Koike, Tetsuo Endoh, T. Makino, Takeshi Ohshima
Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability. IRPS (2022)
Ryo Tamura, N. Watanabe, Hiroki Koike, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Soshi Sato
A novel memory test system with an electromagnet for STT-MRAM testing. NVMTS (2019)
Hiroki Koike, István Kovács, Dragan Marusic, Mikhail E. Muzychuk
Cyclic groups are CI-groups for balanced configurations. Des. Codes Cryptogr. 87 (6) (2019)
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. ISSCC (2019)
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. IEEE J. Solid State Circuits 54 (11) (2019)
Ryo Tamura, I. Mori, N. Watanabe, Hiroki Koike, Tetsuo Endoh
Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system. NVMTS (2018)
Hiroki Koike, Daniel Pellicer, Miguel Raggi, Steve Wilson
Flag Bicolorings, Pseudo-Orientations, and Double Covers of Maps. Electron. J. Comb. 24 (1) (2017)
Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno
An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (2) (2016)
Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE 104 (10) (2016)
Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS (2016)
Hiroki Koike, István Kovács
Isomorphic tetravalent cyclic Haar graphs. Ars Math. Contemp. 7 (1) (2014)
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. IEEE J. Solid State Circuits 48 (6) (2013)
Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS (2012)
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. VLSIC (2012)
Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura
An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O. IEICE Trans. Electron. (6) (2011)
Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura
An electrically adjustable 3-terminal regulator with post-fabrication level-trimming function. ASP-DAC (2010)
Junichi Yamada, Tohru Miwa, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Hidemitsu Mori, Seiichi Takahashi, Hidenori Takeuchi, Takemitsu Kunio
A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers. IEEE J. Solid State Circuits 37 (8) (2002)
Tohru Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Takemitsu Kunio
NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors. IEEE J. Solid State Circuits 36 (3) (2001)
Hideo Toyoshima, Sota Kobayashi, Junichi Yamada, Tohru Miwa, Hiroki Koike, Hidenori Takeuchi, Hidemitsu Mori, Naoki Kasai, Yukihiko Maejima, Nobuhira Tanabe, Toru Tatsumi, Hiromitsu Hada
FeRAM device and circuit technologies fully compatible with advanced CMOS. CICC (2001)
Tohm Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Tom Tatsumi, Yukihiro Maejima, Hiromitsu Hada, Takemitsu Kunio
NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors. CICC (2000)
Tohru Miwa, Junichi Yamada, Yuji Okamoto, Hiroki Koike, Hideo Toyoshiina, Hiromitsu Hada, Yoshihiro Hayashi, Hiroaki Oliizaki, Yoichi Miyasalca, Takemitsu Kunio, Hidenobu Miyamoto, Hideki Gomi, Hiroshi Kitajima
An embedded FeRAM macro cell for a smart card microcontroller. CICC (1998)
Hiroki Koike, Toshio Takeshima, Masahide Takada
A BIST scheme using microprogram ROM for large capacity memories. ITC (1990)