Takashi Ohsawa

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 7

Top Topics

Optimization Algorithm

Bayesian Inference

Top Venues

IEICE Trans. Electron.

Publications

Yaxin Mei, Takashi Ohsawa
A Fully Analog Deep Neural Network Inference Accelerator with Pipeline Registers Based on Master-Slave Switched Capacitors. IEICE Trans. Electron. 106 (9) (2023)
Zian Chen, Takashi Ohsawa
A Low-Cost Training Method of ReRAM Inference Accelerator Chips for Binarized Neural Networks to Recover Accuracy Degradation due to Statistical Variabilities. IEICE Trans. Electron. (8) (2022)
Haoyan Liu, Takashi Ohsawa
Compact Model of Magnetic Tunnel Junctions for SPICE Simulation Based on Switching Probability. IEICE Trans. Electron. (3) (2021)
Ziyue Zhang, Takashi Ohsawa
Array Design of High-Density Emerging Memories Making Clamped Bit-Line Sense Amplifier Compatible with Dummy Cell Average Read Scheme. IEICE Trans. Electron. (8) (2020)
Yue Guan, Takashi Ohsawa
Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm. IEICE Trans. Electron. (11) (2020)
Haoyan Liu, Takashi Ohsawa
User- Friendly Compact Model of Magnetic Tunnel Junctions for Circuit Simulation Based on Switching Probability. VLSI-DAT (2019)
Takashi Ohsawa
A New Read Scheme for High-Density Emerging Memories. IEICE Trans. Electron. (6) (2018)
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. IEEE J. Solid State Circuits 48 (6) (2013)
Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS (2012)
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. VLSIC (2012)
Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh
Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating. IEICE Trans. Electron. (5) (2012)
Takashi Ohsawa, Kosuke Hatsuda, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoki Higashi
Generation of Accurate Reference Current for Data Sensing in High-Density Memories by Averaging Multiple Pairs of Dummy Cells. IEEE J. Solid State Circuits 46 (9) (2011)
Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Tomoaki Shino, Yoshihiro Minami, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe, Shuso Fujii, Tohru Furuyama
Design of a 128-mb SOI DRAM using the floating body cell (FBC). IEEE J. Solid State Circuits 41 (1) (2006)
Kosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa
A 333MHz random cycle DRAM using the floating body cell. CICC (2005)
Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi
Memory design using a one-transistor gain cell on SOI. IEEE J. Solid State Circuits 37 (11) (2002)