Yoshiaki Asao

Publication Activity (10 Years)

Years Active: 1996-2017
Publications (10 Years): 2

Top Topics

Neural Network Model

Memory Requirements

Statistical Model

Top Venues

IEICE Trans. Electron.

Publications

Yoshiaki Asao, Fumio Horiguchi
A Comprehensive Model for Write Disturbance in Resistive Memory Composed of Cross-Point Array. IEICE Trans. Electron. (3) (2017)
Yoshiaki Asao, Fumio Horiguchi
A Precise Model for Cross-Point Memory Array. IEICE Trans. Electron. (1) (2016)
Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe
A 64Mb MRAM with clamped-reference and adequate-reference schemes. ISSCC (2010)
Yoshiaki Asao, Masayoshi Iwayama, Kenji Tsuchida, Akihiro Nitayama, Hiroaki Yoda, Hisanori Aikawa, Sumio Ikegawa, Tatsuya Kishi
A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory. DFT (2008)
Yuui Shimizu, Hisanori Aikawa, Keiji Hosotani, Naoharu Shimomura, Tadashi Kai, Yoshihiro Ueda, Yoshiaki Asao, Yoshihisa Iwata, Kenji Tsuchida, Sumio Ikegawa
MRAM Write Error Categorization with QCKB. MTDT (2006)
Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda
A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. ISSCC (2006)
Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi
Memory design using a one-transistor gain cell on SOI. IEEE J. Solid State Circuits 37 (11) (2002)
Toshiaki Kirihata, Hing Wong, John K. DeBrosse, Yohji Watanabe, Takahiko Hara, Munehiro Yoshida, Matthew R. Wordeman, Shuso Fujii, Yoshiaki Asao, Bo Krsnik
Flexible test mode approach for 256-Mb DRAM. IEEE J. Solid State Circuits 32 (10) (1997)
Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao
Fault-tolerant designs for 256 Mb DRAM. IEEE J. Solid State Circuits 31 (4) (1996)