Shuichi Tahara

Publication Activity (10 Years)

Years Active: 2003-2007
Publications (10 Years): 0

Publications

Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Shuichi Tahara, Naoki Kasai
MRAM Applications Using Unlimited Write Endurance. IEICE Trans. Electron. (10) (2007)
Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai, Hiromitsu Hada, Shuichi Tahara
Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode. IEICE Trans. Electron. (2) (2007)
Eugenio Cantatore, Shuichi Tahara
TD: Emerging Devices Devices and Circuits. ISSCC (2007)
Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara
MRAM Cell Technology for Over 500-MHz SoC. IEEE J. Solid State Circuits 42 (4) (2007)
Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Katsumi Suemitsu, Tomonori Mukai, Kaoru Mori, Ryusuke Nebashi, Shunsuke Fukami, Norikazu Ohshima, Hiromitsu Hada, Nobuyuki Ishiwata, Naoki Kasai, Shuichi Tahara
A 16-Mb Toggle MRAM With Burst Modes. IEEE J. Solid State Circuits 42 (11) (2007)
Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda
A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. ISSCC (2006)
Tsuneo Inaba, Kenji Tsuchida, Tadahiko Sugibayashi, Shuichi Tahara, Hiroaki Yoda
) architecture for a burst operated 1.5V MRAM macro. CICC (2003)