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Kenji Tsuchida
Publication Activity (10 Years)
Years Active: 2003-2019
Publications (10 Years): 2
Top Topics
Stem Cell
Technology Adoption
Predicting Future
Hierarchical Architecture
Top Venues
ISSCC
VLSI-DAT
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Publications
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Katsuhiko Hoya
,
Kosuke Hatsuda
,
Kenji Tsuchida
,
Yohji Watanabe
,
Yusuke Shirota
,
Tatsunori Kanai
A perspective on NVRAM technology for future computing system.
VLSI-DAT
(2019)
Kwangmyoung Rho
,
Kenji Tsuchida
,
Dongkeun Kim
,
Yutaka Shirai
,
Jihyae Bae
,
Tsuneo Inaba
,
Hiromi Noro
,
Hyunin Moon
,
Sungwoong Chung
,
Kazumasa Sunouchi
,
Jinwon Park
,
Kiseon Park
,
Akihito Yamamoto
,
Seoungju Chung
,
Hyeongon Kim
,
Hisato Oyamatsu
,
Jonghoon Oh
23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture.
ISSCC
(2017)
Kenji Tsuchida
,
Tsuneo Inaba
,
Katsuyuki Fujita
,
Yoshihiro Ueda
,
Takafumi Shimizu
,
Yoshiaki Asao
,
Takeshi Kajiyama
,
Masayoshi Iwayama
,
Kuniaki Sugiura
,
Sumio Ikegawa
,
Tatsuya Kishi
,
Tadashi Kai
,
Minoru Amano
,
Naoharu Shimomura
,
Hiroaki Yoda
,
Yohji Watanabe
A 64Mb MRAM with clamped-reference and adequate-reference schemes.
ISSCC
(2010)
Yoshiaki Asao
,
Masayoshi Iwayama
,
Kenji Tsuchida
,
Akihiro Nitayama
,
Hiroaki Yoda
,
Hisanori Aikawa
,
Sumio Ikegawa
,
Tatsuya Kishi
A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory.
DFT
(2008)
Yuui Shimizu
,
Hisanori Aikawa
,
Keiji Hosotani
,
Naoharu Shimomura
,
Tadashi Kai
,
Yoshihiro Ueda
,
Yoshiaki Asao
,
Yoshihisa Iwata
,
Kenji Tsuchida
,
Sumio Ikegawa
MRAM Write Error Categorization with QCKB.
MTDT
(2006)
Yoshihisa Iwata
,
Kenji Tsuchida
,
Tsuneo Inaba
,
Yui Shimizu
,
R. Takizawa
,
Yoshihiro Ueda
,
Tadahiko Sugibayashi
,
Yoshiaki Asao
,
Takeshi Kajiyama
,
Keiji Hosotani
,
Sumio Ikegawa
,
Tadashi Kai
,
M. Nakayama
,
Shuichi Tahara
,
Hiroaki Yoda
A 16Mb MRAM with FORK Wiring Scheme and Burst Modes.
ISSCC
(2006)
Tsuneo Inaba
,
Kenji Tsuchida
,
Tadahiko Sugibayashi
,
Shuichi Tahara
,
Hiroaki Yoda
) architecture for a burst operated 1.5V MRAM macro.
CICC
(2003)