Noboru Sakimura

Publication Activity (10 Years)

Years Active: 2007-2016
Publications (10 Years): 1

Top Topics

Power Dissipation

Associative Memory

Frame Interpolation

Top Venues

IEICE Electron. Express

IEEE J. Emerg. Sel. Topics Circuits Syst.

J. Multiple Valued Log. Soft Comput.

Publications

Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory. J. Multiple Valued Log. Soft Comput. 26 (1-2) (2016)
Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits 50 (2) (2015)
Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express 11 (10) (2014)
Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express 11 (13) (2014)
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. 4 (4) (2014)
Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
Soft-Delay-Error Evaluation in Content-Addressable Memory. ISMVL (2014)
Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. ISCAS (2014)
Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. ISSCC (2014)
Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi
MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. ISCAS (2013)
Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC (2013)
Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. IPSJ Trans. Syst. LSI Des. Methodol. 6 (2013)
Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. Inf. Media Technol. 8 (2) (2013)
Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi
A non-volatile reconfigurable offloader for wireless sensor nodes. SIGARCH Comput. Archit. News 40 (5) (2012)
Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS (2012)
Makoto Miyamura, Shogo Nakaya, Munehiro Tada, Toshitsugu Sakamoto, Koichiro Okamoto, Naoki Banno, Shinji Ishida, Kimihiko Ito, Hiromitsu Hada, Noboru Sakimura, Tadahiko Sugibayashi, Masato Motomura
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS. ISSCC (2011)
Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai
Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros. IEICE Trans. Electron. (4) (2009)
Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai
Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs. IEEE J. Solid State Circuits 44 (8) (2009)
Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito, Yuichi Ito, Sadahiko Miura, Yuko Kato, Kaoru Mori, Yasuaki Ozaki, Yosuke Kobayashi, Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Katsumi Suemitsu, Shunsuke Fukami, Hiromitsu Hada, Tadahiko Sugibayashi, Naoki Kasai
A 90nm 12ns 32Mb 2T1MTJ MRAM. ISSCC (2009)
Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai
Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs. CICC (2008)
Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Shuichi Tahara, Naoki Kasai
MRAM Applications Using Unlimited Write Endurance. IEICE Trans. Electron. (10) (2007)
Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai, Hiromitsu Hada, Shuichi Tahara
Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode. IEICE Trans. Electron. (2) (2007)
Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara
MRAM Cell Technology for Over 500-MHz SoC. IEEE J. Solid State Circuits 42 (4) (2007)
Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Katsumi Suemitsu, Tomonori Mukai, Kaoru Mori, Ryusuke Nebashi, Shunsuke Fukami, Norikazu Ohshima, Hiromitsu Hada, Nobuyuki Ishiwata, Naoki Kasai, Shuichi Tahara
A 16-Mb Toggle MRAM With Burst Modes. IEEE J. Solid State Circuits 42 (11) (2007)