Tetsuo Endoh

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 21

Top Topics

Write Operations

Adaptive Quantization

Cmos Technology

Top Venues

IEEE Trans. Ind. Informatics

IEICE Electron. Express

IEEE J. Solid State Circuits

Publications

Li Zhang, Tao Li, Tetsuo Endoh
Small Area and High Throughput Error Correction Module of STT-MRAM for Object Recognition Systems. IEEE Trans. Ind. Informatics 20 (5) (2024)
Tao Li, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh
Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator". IEEE Trans. Very Large Scale Integr. Syst. 31 (6) (2023)
Tao Li, Yitao Ma, Tetsuo Endoh
Neuromorphic processor-oriented hybrid Q-format multiplication with adaptive quantization for tiny YOLO3. Neural Comput. Appl. 35 (15) (2023)
Tao Li, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh
Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 31 (7) (2023)
Tao Li, Yitao Ma, Tetsuo Endoh
From Algorithm to Module: Adaptive and Energy-Efficient Quantization Method for Edge Artificial Intelligence in IoT Society. IEEE Trans. Ind. Informatics 19 (8) (2023)
Tao Li, Yitao Ma, Ko Yoshikawa, Osamu Nomura, Tetsuo Endoh
Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT. IEEE Trans. Ind. Informatics 18 (5) (2022)
K. Watanabe, T. Shimada, K. Hirose, H. Shindo, D. Kobayashi, Takaho Tanigawa, Shoji Ikeda, Takamitsu Shinada, Hiroki Koike, Tetsuo Endoh, T. Makino, Takeshi Ohshima
Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability. IRPS (2022)
Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. IEEE J. Solid State Circuits 56 (4) (2021)
Tao Li, Yitao Ma, Tetsuo Endoh
A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate. IEEE Access 8 (2020)
Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. VLSI Circuits (2020)
Tao Li, Yitao Ma, Hui Shen, Tetsuo Endoh
FPGA Implementation of Real-Time Pedestrian Detection Using Normalization-Based Validation of Adaptive Features Clustering. IEEE Trans. Veh. Technol. 69 (9) (2020)
Tao Li, Yitao Ma, Tetsuo Endoh
Normalization-Based Validity Index of Adaptive K-Means Clustering for Multi-Solution Application. IEEE Access 8 (2020)
Ryo Tamura, N. Watanabe, Hiroki Koike, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Soshi Sato
A novel memory test system with an electromagnet for STT-MRAM testing. NVMTS (2019)
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. ISSCC (2019)
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. IEEE J. Solid State Circuits 54 (11) (2019)
Ryo Tamura, I. Mori, N. Watanabe, Hiroki Koike, Tetsuo Endoh
Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system. NVMTS (2018)
Tetsuo Endoh
Embedded nonvolatile memory with STT-MRAMs and its application for nonvolatile brain-inspired VLSIs. VLSI-DAT (2017)
Soshi Sato, Kikuo Yamabe, Tetsuo Endoh, Masaaki Niwa
Formation mechanism of concave by dielectric breakdown on silicon carbide metal-oxide-semiconductor capacitor. Microelectron. Reliab. 58 (2016)
Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno
An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (2) (2016)
Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE 104 (10) (2016)
Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS (2016)
Tetsuo Endoh
Nonvolatile logic and memory devices based on spintronics. ISCAS (2015)
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. VLSIC (2015)
Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits 50 (2) (2015)
Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express 11 (10) (2014)
Satoru Tanoi, Tetsuo Endoh
A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs. IEICE Trans. Electron. (5) (2014)
Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme. IEICE Electron. Express 11 (3) (2014)
Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express 11 (13) (2014)
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. 4 (4) (2014)
Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. ISCAS (2014)
Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. ISSCC (2014)
Kazuki Itoh, Tetsuo Endoh
A Novel Alternating Voltage Controlled Current Sensing Method for Suppressing Thermal Dependency. IEICE Trans. Electron. (5) (2014)
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. IEICE Electron. Express 10 (23) (2013)
Tetsuo Endoh
Foreword. IEICE Trans. Electron. (5) (2013)
Hyoungjun Na, Tetsuo Endoh
A High Performance Current Latch Sense Amplifier with Vertical MOSFET. IEICE Trans. Electron. (5) (2013)
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. IEEE J. Solid State Circuits 48 (6) (2013)
Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC (2013)
Yitao Ma, Tadashi Shibata, Tetsuo Endoh
An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications. ISCAS (2013)
Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. ASP-DAC (2012)
Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS (2012)
Hyoungjun Na, Tetsuo Endoh
A Schmitt Trigger Based SRAM with Vertical MOSFET. IEICE Trans. Electron. (5) (2012)
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. VLSIC (2012)
Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. VLSIC (2012)
Hyoungjun Na, Tetsuo Endoh
Current Controlled MOS Current Mode Logic with Auto-Detection of Threshold Voltage Fluctuation. IEICE Trans. Electron. (4) (2012)
Moon-Sik Seo, Tetsuo Endoh
FG Width Scalability of the 3-D Vertical FG NAND Using the Sidewall Control Gate (SCG). IEICE Trans. Electron. (5) (2012)
Yuto Norifusa, Tetsuo Endoh
Evaluation of Performance in Vertical 1T-DRAM and Planar 1T-DRAM. IEICE Trans. Electron. (5) (2012)
Takuya Imamoto, Tetsuo Endoh
Source/Drain Engineering for High Performance Vertical MOSFET. IEICE Trans. Electron. (5) (2012)
Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh
Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating. IEICE Trans. Electron. (5) (2012)
Takeshi Sasaki, Takuya Imamoto, Tetsuo Endoh
Temperature Dependency of Driving Current in High-k/Metal Gate MOSFET and Its Influence on CMOS Inverter Circuit. IEICE Trans. Electron. (5) (2011)
Moon-Sik Seo, Tetsuo Endoh
The Optimum Physical Targets of the 3-Dimensional Vertical FG NAND Flash Memory Cell Arrays with the Extended Sidewall Control Gate (ESCG) Structure. IEICE Trans. Electron. (5) (2011)
Yitao Ma, Tetsuo Endoh, Tadashi Shibata
A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching. ISOCC (2011)
Masashi Kamiyanagi, Takuya Imamoto, Takeshi Sasaki, Hyoungjun Na, Tetsuo Endoh
Verification of Stable Circuit Operation of 180 nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation. IEICE Trans. Electron. (5) (2011)
Masakazu Muraguchi, Yoko Sakurai, Yukihiro Takada, Shintaro Nomura, Kenji Shiraishi, Mitsuhisa Ikeda, Katsunori Makihara, Seiichi Miyazaki, Yasuteru Shigeta, Tetsuo Endoh
Study on Collective Electron Motion in Si-Nano Dot Floating Gate MOS Capacitor. IEICE Trans. Electron. (5) (2011)
Masakazu Muraguchi, Tetsuo Endoh
Study on Impurity Distribution Dependence of Electron-Dynamics in Vertical MOSFET. IEICE Trans. Electron. (5) (2011)
Takuya Imamoto, Takeshi Sasaki, Tetsuo Endoh
Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET with 65 nm CMOS Process. IEICE Trans. Electron. (5) (2011)
Tetsuo Endoh, Masashi Kamiyanagi, Masakazu Muraguchi, Takuya Imamoto, Takeshi Sasaki
The Impact of Current Controlled-MOS Current Mode Logic/Magnetic Tunnel Junction Hybrid Circuit for Stable and High-Speed Operation. IEICE Trans. Electron. (5) (2011)
Yuto Norifusa, Tetsuo Endoh
Impact of Floating Body Type DRAM with the Vertical MOSFET. IEICE Trans. Electron. (5) (2011)
Masakazu Muraguchi, Tetsuo Endoh
Study on Quantum Electro-Dynamics in Vertical MOSFET. IEICE Trans. Electron. (5) (2010)
Tetsuo Endoh, Koji Sakui, Yukio Yasuda
Design of 30 nm FinFETs and Double Gate MOSFETs with Halo Structure. IEICE Trans. Electron. (5) (2010)
Koji Sakui, Tetsuo Endoh
A compact and low power logic design for multi-pillar vertical MOSFETs. ISCAS (2010)
Masashi Kamiyanagi, Fumitaka Iga, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit. IEICE Trans. Electron. (5) (2010)
Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits. IEICE Trans. Electron. (5) (2010)
Tetsuo Endoh, Koji Sakui, Yukio Yasuda
Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET. IEICE Trans. Electron. (5) (2010)
Masakazu Muraguchi, Yukihiro Takada, Shintaro Nomura, Tetsuo Endoh, Kenji Shiraishi
Importance of the Electronic State on the Electrode in Electron Tunneling Processes between the Electrode and the Quantum Dot. IEICE Trans. Electron. (5) (2010)
Tetsuo Endoh, Yuto Norifusa
Study of Self-Heating Phenomena in Si Nano Wire MOS Transistor. IEICE Trans. Electron. (5) (2009)
Tetsuo Endoh, Masashi Kamiyanagi
Novel Concept Dynamic Feedback MCML Technique for High-Speed and High-Gain MCML Type Latch. IEICE Trans. Electron. (5) (2009)
Tetsuo Endoh, Yuto Norifusa
Scalability of Vertical MOSFETs in Sub-10 nm Generation and Its Mechanism. IEICE Trans. Electron. (5) (2009)
Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. DATE (2009)
Tetsuo Endoh, Yuto Momma
Study of 30-nm Double-Gate MOSFET with Halo Implantation Technology Using a Two-Dimensional Device Simulator. IEICE Trans. Electron. (5) (2007)
Tetsuo Endoh, Kazuyuki Hirose, Kenji Shiraishi
Physical Origin of Stress-Induced Leakage Currents in Ultra-Thin Silicon Dioxide Films. IEICE Trans. Electron. (5) (2007)
Tetsuo Endoh, Kazuhisa Sunaga, Hiroshi Sakuraba, Fujio Masuoka
An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current. IEEE J. Solid State Circuits 36 (1) (2001)
Akira Tanabe, Masato Umetani, Ikuo Fujiwara, Takayuki Ogura, Kotaro Kataoka, Masao Okihara, Hiroshi Sakuraba, Tetsuo Endoh, Fujio Masuoka
0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation. IEEE J. Solid State Circuits 36 (6) (2001)
Kazuhisa Sunaga, Tetsuo Endoh, Hiroshi Sakuraba, Fujio Masuoka
An on-chip 96.5% current efficiency CMOS linear regulator. ASP-DAC (2001)
Tetsuo Endoh, Katsuhisa Shinmei, Hiroshi Sakuraba, Fujio Masuoka
New three-dimensional memory array architecture for future ultrahigh-density DRAM. IEEE J. Solid State Circuits 34 (4) (1999)
Seiichi Aritome, Riichiro Shirota, Gertjan Hemink, Tetsuo Endoh, Fujio Masuoka
Reliability issues of flash memory cells. Proc. IEEE 81 (5) (1993)