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An on-chip 96.5% current efficiency CMOS linear regulator.
Kazuhisa Sunaga
Tetsuo Endoh
Hiroshi Sakuraba
Fujio Masuoka
Published in:
ASP-DAC (2001)
Keyphrases
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high speed
low cost
analog vlsi
steady state
circuit design
cmos image sensor
single chip
low voltage
control system
digital camera
high efficiency
linear systems
vlsi implementation