An on-chip 96.5% current efficiency CMOS linear regulator.

Kazuhisa Sunaga Tetsuo Endoh Hiroshi Sakuraba Fujio Masuoka

Published in: ASP-DAC (2001)

Keyphrases

high speed
low cost
analog vlsi
steady state
circuit design
cmos image sensor
single chip
low voltage
control system
digital camera
high efficiency
linear systems
vlsi implementation