A compact and low power logic design for multi-pillar vertical MOSFETs.
Koji SakuiTetsuo EndohPublished in: ISCAS (2010)
Keyphrases
- low power
- logic circuits
- high speed
- power consumption
- low cost
- single chip
- low power consumption
- gate array
- vlsi architecture
- digital signal processing
- design process
- high power
- delay insensitive
- cmos technology
- power reduction
- real time
- power dissipation
- signal processing
- mixed signal
- design methodology
- general purpose