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Koji Sakui
Publication Activity (10 Years)
Years Active: 1994-2023
Publications (10 Years): 7
Top Topics
Ibm Eservertm
Flash Memory
Silicon Dioxide
Storage Devices
Top Venues
IMW
IRPS
3DIC
VLSI Technology and Circuits
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Publications
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Norio Chujo
,
Koji Sakui
,
Shinji Sugatani
,
Hiroyuki Ryoson
,
Tomoji Nakamura
,
Takayuki Ohba
Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WoW and CoW to Provide TB/s Bandwidth with Lowest Bit Access Energy.
VLSI Technology and Circuits
(2023)
Koji Sakui
,
Masakazu Kakumu
,
Nozomu Harada
Dynamic Flash Memory with Fast Block Refresh.
NVMTS
(2022)
Zhwen Chen
,
Young-Suk Kim
,
Tadashi Fukuda
,
Koji Sakui
,
Takayuki Ohba
,
Tatsuji Kobayashi
,
Takashi Obara
Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs.
IRPS
(2021)
Yisuo Li
,
Ken'ichi Kanazawa
,
Tetsuo Izawa
,
Koji Sakui
,
Georg Strof
,
Oskar Baumgartner
,
Gerhard Rzepa
,
Markus Karner
,
Zlatan Stanojevic
,
Nozomu Harada
,
Fujio Masuoka
1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.
IMW
(2021)
Koji Sakui
,
Nozomu Harada
Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT).
IMW
(2021)
Koji Sakui
,
Takayuki Ohba
High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology.
3DIC
(2019)
Koji Sakui
,
Takayuki Ohba
Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation : High Speed, Low Power, and Ultra-small Operating Platform.
CICC
(2019)
Tetsuo Endoh
,
Koji Sakui
,
Yukio Yasuda
Design of 30 nm FinFETs and Double Gate MOSFETs with Halo Structure.
IEICE Trans. Electron.
(5) (2010)
Koji Sakui
,
Tetsuo Endoh
A compact and low power logic design for multi-pillar vertical MOSFETs.
ISCAS
(2010)
Tetsuo Endoh
,
Koji Sakui
,
Yukio Yasuda
Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET.
IEICE Trans. Electron.
(5) (2010)
Ken Takeuchi
,
Shinji Satoh
,
Ken-ichi Imamiya
,
Koji Sakui
A source-line programming scheme for low-voltage operation NAND flash memories.
IEEE J. Solid State Circuits
35 (5) (2000)
Hironori Banba
,
Hitoshi Shiga
,
Akira Umezawa
,
Takeshi Miyaba
,
Toru Tanzawa
,
Shigeru Atsumi
,
Koji Sakui
A CMOS bandgap reference circuit with sub-1-V operation.
IEEE J. Solid State Circuits
34 (5) (1999)
Kenichi Imamiya
,
Yoshihisa Sugiura
,
Hiroshi Nakamura
,
Toshihiko Himeno
,
Ken Takeuchi
,
Tamio Ikehashi
,
Kazushige Kanda
,
Koji Hosono
,
Riichiro Shirota
,
Seiichi Aritome
,
Kazuhiro Shimizu
,
Kazuo Hatakeyama
,
Koji Sakui
, 256-Mbit NAND flash with shallow trench isolation technology.
IEEE J. Solid State Circuits
34 (11) (1999)
Ken Takeuchi
,
Shinji Satoh
,
Tomoharu Tanaka
,
Ken-ichi Imamiya
,
Koji Sakui
cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories.
IEEE J. Solid State Circuits
34 (5) (1999)
Jin-Ki Kim
,
Koji Sakui
,
Sung-Soo Lee
,
Yasuo Itoh
,
Suk-Chon Kwon
,
Kazuhisa Kanazawa
,
Ki-Jun Lee
,
Hiroshi Nakamura
,
Kang-Young Kim
,
Toshihiko Himeno
,
Jang-Rae Kim
,
Kazushige Kanda
,
Tae-Sung Jung
,
Yoichi Oshima
,
Kang-Deog Suh
,
Kazuhiko Hashimoto
,
Sung-Tae Ahn
,
Junichi Miyamoto
64-Mb NAND flash memory achieving 180 ns/Byte effective program speed.
IEEE J. Solid State Circuits
32 (5) (1997)
Tomoharu Tanaka
,
Yoshiyuki Tanaka
,
Hiroshi Nakamura
,
Koji Sakui
,
Hideko Oodaira
,
Riichiro Shirota
,
Kazunori Ohuchi
,
Fujio Masuoka
,
Hisashi Hara
A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory.
IEEE J. Solid State Circuits
29 (11) (1994)