Hiroshi Nakamura

ORCID

Publication Activity (10 Years)

Years Active: 1984-2024
Publications (10 Years): 52

Top Venues

IEICE Trans. Inf. Syst.

IECON

ISSCC

MCSoC

Publications

Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura
SFQ counter-based precomputation for large-scale cryogenic VQE machines. CoRR (2024)
Satoshi Okada, Houda Jmila, Kunio Akashi, Takuho Mitsunaga, Yuji Sekiya, Hideki Takase, Gregory Blanc, Hiroshi Nakamura
XAI-driven Adversarial Attacks on Network Intrusion Detectors. EICC (2024)
Ai Nozaki, Takuya Kojima, Hiroshi Nakamura, Hideki Takase
MLIR-Based Homomorphic Encryption Compiler for GPU. HEART (2024)
Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura
Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines. IEEE Comput. Archit. Lett. 23 (1) (2024)
Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura
A Scalable Mapping Method for Elastic CGRAs. IPDPS (Workshops) (2024)
Kaito Kutsuna, Takuya Kojima, Hideki Takase, Hiroshi Nakamura
An Area-Efficient Coarse-Grained Reconfigurable Array Design for Approximate Computing. MCSoC (2023)
Yusuke Kanamori, Yusuke Yamasaki, Shintaro Hosoai, Hiroshi Nakamura, Hideki Takase
An asynchronous federated learning focusing on updated models for decentralized systems with a practical framework. COMPSAC (2023)
Satoshi Okada, Kunio Akashi, Daisuke Miyamoto, Yuji Sekiya, Hideki Takase, Hiroshi Nakamura
Memory-saving LDoS Attacker Detection Algorithms in Zigbee Network. J. Inf. Process. 31 (2023)
Siyi Hu, Masaaki Kondo, Yuan He, Ryuichi Sakamoto, Hao Zhang, Jun Zhou, Hiroshi Nakamura
An edge re-ordering based acceleration architecture for improving data locality in graph analytics applications. Microprocess. Microsystems 102 (2023)
Siyi Hu, Makiko Ito, Takahide Yoshikawa, Yuan He, Hiroshi Nakamura, Masaaki Kondo
Adaptive Lossy Data Compression Extended Architecture for Memory Bandwidth Conservation in SpMV. IEICE Trans. Inf. Syst. 106 (12) (2023)
Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura
Inter-temperature Bandwidth Reduction in Cryogenic QAOA Machines. CoRR (2023)
Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura
ILP Based Mapping for Elastic CGRAs. RTCSA (2023)
Toyotaro Suzumura, Akiyoshi Sugiki, Hiroyuki Takizawa, Akira Imakura, Hiroshi Nakamura, Kenjiro Taura, Tomohiro Kudoh, Toshihiro Hanawa, Yuji Sekiya, Hill Hiroki Kobayashi, Shin Matsushima, Yohei Kuga, Ryo Nakamura, Renhe Jiang, Junya Kawase, Masatoshi Hanai, Hiroshi Miyazaki, Tsutomu Ishizaki, Daisuké Shimotoku, Daisuke Miyamoto, Kento Aida, Atsuko Takefusa, Takashi Kurimoto, Koji Sasayama, Naoya Kitagawa, Ikki Fujiwara, Yusuke Tanimura, Takayuki Aoki, Toshio Endo, Satoshi Ohshima, Keiichiro Fukazawa, Susumu Date, Toshihiro Uchibayashi
mdx: A Cloud Platform for Supporting Data Science and Cross-Disciplinary Research Collaborations. CoRR (2022)
Siyi Hu, Masaaki Kondo, Yuan He, Ryuichi Sakamoto, Hao Zhang, Jun Zhou, Hiroshi Nakamura
GraphDEAR: An Accelerator Architecture for Exploiting Cache Locality in Graph Analytics Applications. PDP (2022)
Kiyotaka Hayami, Daichi Kawamoto, Mitsuru Shinagawa, Masayuki Makino, Hiroshi Nakamura, Naoyuki Honma
Improvement of Signal Power in Intrabody Communication Using an Impedance Adjustment Circuit. GCCE (2022)
Toyotaro Suzumura, Akiyoshi Sugiki, Hiroyuki Takizawa, Akira Imakura, Hiroshi Nakamura, Kenjiro Taura, Tomohiro Kudoh, Toshihiro Hanawa, Yuji Sekiya, Hill Hiroki Kobayashi, Yohei Kuga, Ryo Nakamura, Renhe Jiang, Junya Kawase, Masatoshi Hanai, Hiroshi Miyazaki, Tsutomu Ishizaki, Daisuké Shimotoku, Daisuke Miyamoto, Kento Aida, Atsuko Takefusa, Takashi Kurimoto, Koji Sasayama, Naoya Kitagawa, Ikki Fujiwara, Yusuke Tanimura, Takayuki Aoki, Toshio Endo, Satoshi Ohshima, Keiichiro Fukazawa, Susumu Date, Toshihiro Uchibayashi
mdx: A Cloud Platform for Supporting Data Science and Cross-Disciplinary Research Collaborations. DASC/PiCom/CBDCom/CyberSciTech (2022)
Satoshi Okada, Daisuke Miyamoto, Yuji Sekiya, Hiroshi Nakamura
New LDoS Attack in Zigbee Network and its Possible Countermeasures. SMARTCOMP (2021)
Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura
Multi-objective Reinforcement Learning for Energy Harvesting Wireless Sensor Nodes. MCSoC (2021)
Yuta Suzuki, Ryuichi Sakamoto, Hiroshi Nakamura
Dynamic Power Management for 5G Small Cell Base Station. COMSNETS (2021)
Satoshi Okada, Daisuke Miyamoto, Yuji Sekiya, Hideki Takase, Hiroshi Nakamura
LDoS Attacker Detection Algorithms in Zigbee Network. iThings/GreenCom/CPSCom/SmartData/Cybermatics (2021)
Takashi Nakada, Hiroyuki Yanagihashi, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura
An Energy-Efficient Task Scheduling for Near Real-Time Systems on Heterogeneous Multicore Processors. IEICE Trans. Inf. Syst. (2) (2020)
Tomoya Yamashita, Daisuke Miyamoto, Yuji Sekiya, Hiroshi Nakamura
Slow Scan Attack Detection Based on Communication Behavior. ICCNS (2020)
Naoya Takahashi, Yoshiki Matsui, Sotaro Sawa, Daichi Kawamoto, Mitsuru Shinagawa, Kohei Hamamura, Hiroshi Nakamura, Naohiro Shimizu, Masaya Sugino
Electric Field Communication using a Wide Metal Plate as the Transmission Path. GCCE (2020)
Noboru Shibata, Takahisa Kawabe, Taira Shibuya, Mario Sako, Kosuke Yanagidaira, Toshifumi Hashimoto, Hiroki Date, Manabu Sato, Tomoki Nakagawa, Junji Musha, Takatoshi Minamoto, Kazushige Kanda, Mizuki Uda, Dai Nakamura, Katsuaki Sakurai, Takahiro Yamashita, Jieyun Zhou, Ryoichi Tachibana, Teruo Takagiwa, Takahiro Sugimoto, Masatsugu Ogawa, Yusuke Ochi, Takahiro Shimizu, Kazuaki Kawaguchi, Masatsugu Kojima, Takeshi Ogawa, Tomoharu Hashiguchi, Ryo Fukuda, Masami Masuda, Koichi Kawakami, Tadashi Someya, Yasuyuki Kajitani, Yuuki Matsumoto, Jun Nakai, Jumpei Sato, Namasivayam Raghunathan, Yee Lih Koh, Shuo Chen, Juan Lee, Hiroaki Nasu, Hiroshi Sugawara, Koji Hosono, Toshiki Hisada, Hiroshi Nakamura, Osamu Nagao, Naoki Kobayashi, Makoto Miakashi, Yasushi Nagadomi, Tomoaki Nakano
A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology. IEEE J. Solid State Circuits 55 (1) (2020)
Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura
Power Management of Wireless Sensor Nodes with Coordinated Distributed Reinforcement Learning. ICCD (2019)
Yoshiki Matsui, Kenta Nezu, Naoya Takahashi, Koki Yoshioka, Mitsuru Shinagawa, Kohei Hamamura, Hiroshi Nakamura, Naohiro Shimizu
Electric Field Communication using a Car Body as a Transmission Medium. ICST (2019)
Kaede Torii, Shota Nakashima, Hiroshi Nakamura, Tetsuo Ooyagi, Kanya Tanaka, Hiroyuki Yagami
Distinction of Heart Sound and Respiratory Sound Using Body Conduction Sound Sensor Based on HPSS. ACIT (2019)
Noboru Shibata, Kazushige Kanda, Takahiro Shimizu, Jun Nakai, Osamu Nagao, Naoki Kobayashi, Makoto Miakashi, Yasushi Nagadomi, Takeshi Nakano, Takahisa Kawabe, Taira Shibuya, Mario Sako, Kosuke Yanagidaira, Toshifumi Hashimoto, Hiroki Date, Manabu Sato, Tomoki Nakagawa, H. Takamoto, Junji Musha, Takatoshi Minamoto, Mizuki Uda, Dai Nakamura, Katsuaki Sakurai, Takahiro Yamashita, Jieyun Zhou, Ryoichi Tachibana, Teruo Takagiwa, Takahiro Sugimoto, Mikio Ogawa, Yusuke Ochi, Kazuaki Kawaguchi, Masatsugu Kojima, Takeshi Ogawa, Tomoharu Hashiguchi, Ryo Fukuda, Masami Masuda, Koichi Kawakami, Tadashi Someya, Yasuyuki Kajitani, Yuuki Matsumoto, Naohito Morozumi, Jumpei Sato, Namas Raghunathan, Yee Lih Koh, Shuo Chen, Juan Lee, Hiroaki Nasu, Hiroshi Sugawara, Koji Hosono, Toshiki Hisada, T. Kaneko, Hiroshi Nakamura
A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology. ISSCC (2019)
Chang Hua Siau, Kwang-Ho Kim, Seungpil Lee, Katsuaki Isobe, Noboru Shibata, Kapil Verma, Takuya Ariki, Jason Li, Jong Yuh, Anirudh Amarnath, Qui Nguyen, Ohwon Kwon, Stanley Jeong, Heguang Li, Hua-Ling Hsu, Taiyuan Tseng, Steve Choi, Siddhesh Darne, Pradeep Anantula, Alex Yap, Hardwell Chibvongodze, Hitoshi Miwa, Minoru Yamashita, Mitsuyuki Watanabe, Koichiro Hayashi, Yosuke Kato, Toru Miwa, Jang Yong Kang, Masatoshi Okumura, Naoki Ookuma, Muralikrishna Balaga, Venky Ramachandra, Aki Matsuda, Swaroop Kulkarni, Raghavendra Rachineni, Pai K. Manjunath, Masahito Takehara, Anil Pai, Srinivas Rajendra, Toshiki Hisada, Ryo Fukuda, Naoya Tokiwa, Kazuaki Kawaguchi, Masashi Yamaoka, Hiromitsu Komai, Takatoshi Minamoto, Masaki Unno, Susumu Ozawa, Hiroshi Nakamura, Tomoo Hishida, Yasuyuki Kajitani, Lei Lin
A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology. ISSCC (2019)
Hiroshi Maejima, Kazushige Kanda, Susumu Fujimura, Teruo Takagiwa, Susumu Ozawa, Jumpei Sato, Yoshihiko Shindo, Manabu Sato, Naoaki Kanagawa, Junji Musha, Satoshi Inoue, Katsuaki Sakurai, Naohito Morozumi, Ryo Fukuda, Yuui Shimizu, Toshifumi Hashimoto, Xu Li, Yuki Shimizu, Kenichi Abe, Tadashi Yasufuku, Takatoshi Minamoto, Hiroshi Yoshihara, Takahiro Yamashita, Kazuhiko Satou, Takahiro Sugimoto, Fumihiro Kono, Mitsuhiro Abe, Tomoharu Hashiguchi, Masatsugu Kojima, Yasuhiro Suematsu, Takahiro Shimizu, Akihiro Imamoto, Naoki Kobayashi, Makoto Miakashi, Kouichirou Yamaguchi, Sanad Bushnaq, Hicham Haibi, Masatsugu Ogawa, Yusuke Ochi, Kenro Kubota, Taichi Wakui, Dong He, Weihan Wang, Hiroe Minagawa, Tomoko Nishiuchi, Hao Nguyen, Kwang-Ho Kim, Ken Cheah, Yee Lih Koh, Feng Lu, Venky Ramachandra, Srinivas Rajendra, Steve Choi, Keyur Payak, Namas Raghunathan, Spiros Georgakis, Hiroshi Sugawara, Seungpil Lee, Takuya Futatsuyama, Koji Hosono, Noboru Shibata, Toshiki Hisada, Tetsuya Kaneko, Hiroshi Nakamura
A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology. ISSCC (2018)
Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation. IEICE Trans. Inf. Syst. (10) (2017)
Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano
The Design and Implementation of Scalable Deep Neural Network Accelerator Cores. MCSoC (2017)
Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano
Scalable deep neural network accelerator cores with cubic integration using through chip interface. ISOCC (2017)
Muhammad Khairul Nizar Bin Khairuddin, Kazuhiro Nakamoto, Hiroshi Nakamura, Kanya Tanaka, Shota Nakashima
Heart Rate and Heart Rate Variability Measuring System by Using Smartphone. ACIT/CSII/BCD (2017)
Hiroshi Nakamura, Masaru Nakano
Scenario Analysis for Clean Energy Vehicles in UK Considering Introduction of Renewable Energy Sources. Int. J. Autom. Technol. 11 (4) (2017)
Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki
Building block multi-chip systems using inductive coupling through chip interface. ISOCC (2017)
Toshimasa Miyazaki, Naoki Kamiya, Hiroshi Nakamura, Yuki Yokokura, Kiyoshi Ohishi
Dual notch-type high-order frinction-free force observers for force sensorless fine force control. IECON (2017)
Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Nakamura, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi
Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors. VLSI-SoC (2017)
Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura
Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning. ACM Trans. Embed. Comput. Syst. 16 (5s) (2017)
Hiroshi Nakamura, Kiyoshi Ohishi, Yuki Yokokura, Toshimasa Miyazaki, Akifumi Tsukamoto
Fine force control without force sensor based on reaction force estimation system considering static friction and kinetic friction. IECON (2016)
Takashi Nakada, Tomoki Hatanaka, Hiroshi Nakamura, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis. VLSI-SoC (2016)
Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC (2016)
Takashi Nakada, Hiroshi Nakamura, Toshifumi Nakamoto, Toru Shimizu
Normally-off power management for sensor nodes of global navigation satellite system. ISOCC (2016)
Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip. IEICE Trans. Inf. Syst. (12) (2016)
Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Trans. Electron. (8) (2016)
Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
Runtime multi-optimizations for energy efficient on-chip interconnections1. ICCD (2015)
Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. IEICE Trans. Electron. (7) (2015)
Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura
Energy-Efficient Continuous Task Scheduling for Near Real-Time Periodic Tasks. DSDIS (2015)
Shinobu Miwa, Hiroshi Nakamura
Profile-based power shifting in interconnection networks with on/off links. SC (2015)
Yoshiyasu Takase, Hiroshi Nakamura, Minoru Koga, Toru Shikayama, Akihito Toyota
Position sensorless control with accelerometer for linear and curvilinear synchronous motor. IECON (2015)
Hiroshi Nakamura, Satoshi Ono
Suggestion-based interactive video digest design by user-system cooperative evolution. CEC (2015)
Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. ICCD (2015)
Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. ISSoC (2014)
Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. ASP-DAC (2014)
Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
Design Aid of Multi-core Embedded Systems with Energy Model. Inf. Media Technol. 9 (4) (2014)
Shinobu Miwa, Sho Aita, Hiroshi Nakamura
Performance estimation of high performance computing systems with Energy Efficient Ethernet technology. Comput. Sci. Res. Dev. 29 (3-4) (2014)
Yoshiyasu Takase, Hiroshi Nakamura, Takashi Mamba, Fei Zhao
Proposal of position sensorless control and torque ripple compensation based on torque sensor feedback. IECON (2014)
Shinobu Miwa, Takara Inoue, Hiroshi Nakamura
Area-Efficient Microarchitecture for Reinforcement of Turbo Mode. IEICE Trans. Inf. Syst. (5) (2014)
Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura
Design and evaluation of fine-grained power-gating for embedded microprocessors. DATE (2014)
Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa
Normally-off computing project: Challenges and opportunities. ASP-DAC (2014)
Hiroshi Nakamura, Satoshi Ono
Video summarization support by Interactive Evolutionary Computation. SCIS&ISIS (2014)
Masaki Higashino, Hiroshi Fujimoto, Yoshiyasu Takase, Hiroshi Nakamura
Step climbing control of wheeled robot based on slip ratio taking account of work load shift by anti-dive force of suspensions and accerelation. AMC (2014)
Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu
Data-aware power management for periodic real-time systems with non-volatile memory. NVMSA (2014)
Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33 (6) (2013)
Takashi Nakada, Shinobu Miwa, Keisuke Y. Yano, Hiroshi Nakamura
Performance modeling for designing NoC-based multiprocessors. RSP (2013)
Masaki Higashino, Hiroshi Fujimoto, Yoshiyasu Takase, Hiroshi Nakamura
Proposal of step climbing of wheeled robot using slip ratio control. IECON (2013)
Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips (2013)
Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
Predict-More Router: A Low Latency NoC Router with More Route Predictions. IPDPS Workshops (2013)
Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki
Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Trans. Electron. (4) (2013)
Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE (2013)
Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Naoya Maruyama
Integrating Multi-GPU Execution in an OpenACC Compiler. ICPP (2013)
Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
McRouter: Multicast within a router for high performance network-on-chips. PACT (2013)
Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL (2013)
Toshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping. ICCD (2013)
Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium (2013)
Yuetsu Kodama, Satoshi Itoh, Toshiyuki Shimizu, Satoshi Sekiguchi, Hiroshi Nakamura, Naohiko Mori
Imbalance of CPU temperatures in a blade system and its impact for power consumption of fans. Clust. Comput. 16 (1) (2013)
Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura
Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC (2012)
Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura
Communication Library to Overlap Computation and Communication for OpenCL Application. IPDPS Workshops (2012)
Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT (2012)
Yuan He, Hiroki Matsutani, Hiroshi Sasaki, Hiroshi Nakamura
Adaptive Data Compression on 3D Network-on-Chips. Inf. Media Technol. 7 (1) (2012)
Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura
A novel power-gating scheme utilizing data retentiveness on caches. ACM Great Lakes Symposium on VLSI (2012)
Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
Stepwise sleep depth control for run-time leakage power saving. ACM Great Lakes Symposium on VLSI (2012)
Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating. ISQED (2012)
Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL (2012)
Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, Hiroshi Nakamura
Scalability-based manycore partitioning. PACT (2012)
Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo
Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC (2011)
Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. COOL Chips (2011)
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT (2011)
Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. Inf. Media Technol. 6 (4) (2011)
Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro 31 (6) (2011)
Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (4) (2011)
Seidai Takeda, Kyundong Kim, Hiroshi Nakamura, Kimiyoshi Usami
Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura
On-chip detection methodology for break-even time of power gated function units. ISLPED (2011)
Satoshi Itoh, Yuetsu Kodama, Hiroshi Shimizu, Satoshi Sekiguchi, Hiroshi Nakamura, Naohiko Mori
Power consumption and efficiency of cooling in a Data Center. GRID (2010)
Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
Adaptive power gating for function units in a microprocessor. ISQED (2010)
Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS (2010)
Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC (2010)
Yuetsu Kodama, Satoshi Itoh, Toshiyuki Shimizu, Satoshi Sekiguchi, Hiroshi Nakamura, Naohiko Mori
Power Reduction Scheme of Fans in a Blade System by Considering the Imbalance of CPU Temperatures. GreenCom/CPSCom (2010)

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Hiroshi Nakamura