Kimiyoshi Usami

Publication Activity (10 Years)

Years Active: 1990-2024
Publications (10 Years): 20

Top Topics

Cmos Technology

Energy Efficient

Top Venues

IEICE Trans. Electron.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho
Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations. IEEE Trans. Very Large Scale Integr. Syst. 32 (1) (2024)
Aika Kamei, Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho
A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 31 (4) (2023)
Kimiyoshi Usami, Songxiang Wang, Kaito Nagai, Giovanna Latronico, Paolo Mele
A 200mV Operable On-Chip Temperature Sensor for IoT Devices Powered by Energy Harvesters with Ultra-Low Output Voltage. IoTaIS (2023)
Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho, Kimiyoshi Usami, Taku Umebayashi
A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing. VLSI Technology and Circuits (2023)
Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano
Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations. NorCAS (2022)
Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops. MCSoC (2021)
Yoshinori Ono, Kimiyoshi Usami
Energy Efficient Approximate Storing of Image Data for MTJ Based Non-Volatile Flip-Flops and MRAM. IEICE Trans. Electron. (7) (2021)
Yoshinori Ono, Kimiyoshi Usami
Energy Efficient Approximate Storing of Image Data for MTJ Based Non-volatile Memory. NVMSA (2020)
Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda
Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization. COOL CHIPS (2020)
Kimiyoshi Usami, Junya Akaike, Sosuke Akiba, Masaru Kudo, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami
Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application. NVMSA (2018)
Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops. ReConFig (2018)
Masaru Kudo, Kimiyoshi Usami
Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. NVMSA (2017)
Hayate Okuhara, Yu Fujita, Kimiyoshi Usami, Hideharu Amano
Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET. IEEE Trans. Very Large Scale Integr. Syst. 25 (4) (2017)
Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano
Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI. VLSI-SoC (Selected Papers) (2017)
Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki
Building block multi-chip systems using inductive coupling through chip interface. ISOCC (2017)
Yusuke Yoshida, Kimiyoshi Usami, Hideharu Amano
Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. ISOCC (2017)
Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano
Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI. VLSI-SoC (2017)
Yusuke Yoshida, Kimiyoshi Usami
Energy-Efficient Standard Cell Memory with Optimized Body-Bias Separation in Silicon-on-Thin-BOX (SOTB). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano
Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems. IEICE Trans. Electron. (8) (2016)
Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Trans. Electron. (8) (2016)
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano
A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control. COOL Chips (2015)
Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. IEICE Trans. Electron. (7) (2015)
Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. IEICE Trans. Electron. (7) (2015)
Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, Hideharu Amano
An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET. ISLPED (2015)
Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. ISSoC (2014)
Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. ASP-DAC (2014)
Shiro Kamohara, Nobuyuki Sugii, Koichiro Ishibashi, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham
A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode. Hot Chips Symposium (2014)
Yu Fujita, Kimiyoshi Usami, Hideharu Amano
A Thermal Management System for Building Block Computing Systems. MCSoC (2014)
Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. COOL Chips (2014)
Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura
Design and evaluation of fine-grained power-gating for embedded microprocessors. DATE (2014)
Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33 (6) (2013)
Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips (2013)
Kimiyoshi Usami
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki
Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Trans. Electron. (4) (2013)
Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL (2013)
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. VLSI-DAT (2013)
Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium (2013)
Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC (2012)
Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT (2012)
Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano
Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router. MCSoC (2012)
Weihan Wang, Yuya Ohta, Yoshifumi Ishii, Kimiyoshi Usami, Hideharu Amano
Trade-off analysis of fine-grained power gating methods for functional units in a CPU. COOL Chips (2012)
Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
Stepwise sleep depth control for run-time leakage power saving. ACM Great Lakes Symposium on VLSI (2012)
Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating. ISQED (2012)
Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL (2012)
Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami
Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction. ARC (2011)
Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo
Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC (2011)
Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. COOL Chips (2011)
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT (2011)
Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. Inf. Media Technol. 6 (4) (2011)
Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro 31 (6) (2011)
Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (4) (2011)
Seidai Takeda, Kyundong Kim, Hiroshi Nakamura, Kimiyoshi Usami
Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura
On-chip detection methodology for break-even time of power gated function units. ISLPED (2011)
Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
Adaptive power gating for function units in a microprocessor. ISQED (2010)
Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS (2010)
Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC (2010)
Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano
Cache Controller Design on Ultra Low Leakage Embedded Processors. ARCS (2009)
Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design (2009)
Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD (2008)
Jerry Frenkil, Ken Choi, Kimiyoshi Usami
Power Gating for Ultra-low Leakage: Physics, Design, and Analysis. DATE (2008)
Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano
Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. FPT (2008)
Kimiyoshi Usami
Overview on Low Power SoC Design Technology. ASP-DAC (2007)
Naoaki Ohkubo, Kimiyoshi Usami
Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Naoaki Ohkubo, Kimiyoshi Usami
Delay modeling and static timing analysis for MTCMOS circuits. ASP-DAC (2006)
Kimiyoshi Usami, Naoaki Ohkubo
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. ICCD (2006)
Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa
Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak
Code Coverage-Based Power Estimation Techniques for Microprocessors. J. Circuits Syst. Comput. 11 (5) (2002)
Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa
Automated selective multi-threshold design for ultra-low standby applications. ISLPED (2002)
Kimiyoshi Usami, Mutsunori Igarashi
Low-power design methodology and applications utilizing dual supply voltages. ASP-DAC (2000)
Naoyuki Kawabe, Kimiyoshi Usami
Low-power technique for on-chip memory using biased partitioning and access concentration. CICC (2000)
Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak
Function-level power estimation methodology for microprocessors. DAC (2000)
Kimiyoshi Usami, Mutsunori Igarashi, Fumihiro Minami, Takashi Ishikawa, Masahiro Kanazawa, Makoto Ichida, Kazutaka Nogami
Automated low-power technique exploiting multiple supply voltages applied to a media processor. IEEE J. Solid State Circuits 33 (3) (1998)
Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi
A Clock-Gating Method for Low-Power LSI Design. ASP-DAC (1998)
Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. DAC (1998)
Mototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda
A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. CICC (1998)
Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama
A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. IEEE J. Solid State Circuits 33 (11) (1998)
Mutsunori Igarashi, Kimiyoshi Usami, Kazutaka Nogami, Fumihiro Minami, Yukio Kawasaki, Takahiro Aoki, Midori Takano, Chiharo Mizuno, Takashi Ishikawa, Masahiro Kanazawa, Shinji Sonoda, Makoto Ichida, Naoyuki Hatanaka
A low-power design method using multiple supply voltages. ISLPED (1997)
Kimiyoshi Usami, Mark Horowitz
Clustered voltage scaling technique for low-power design. ISLPD (1995)
Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori
Datapath Generator Based on Gate-Level Symbolic Layout. DAC (1990)