Fumihiko Sano

Publication Activity (10 Years)

Years Active: 1996-2003
Publications (10 Years): 0

Publications

Fumihiko Sano, Kenji Ohkuma, Hideo Shimizu, Shinichi Kawamura
On the Security of Nested SPN Cipher against the Differential and Linear Cryptanalysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2003)
Kenji Ohkuma, Hideo Shimizu, Fumihiko Sano, Shin-ichi Kawamura
Security Assessment of Hierocrypt and Rijndael against the Differential and Linear Cryptanalysis (Extended Abstract). IACR Cryptol. ePrint Arch. 2001 (2001)
Kenji Ohkuma, Hirofumi Muratani, Fumihiko Sano, Shin-ichi Kawamura
The Block Cipher Hierocrypt. Selected Areas in Cryptography (2000)
Fumihiko Sano, Masanobu Koike, Shin-ichi Kawamura, Masue Shiba
Performance Evaluation of AES Finalists on the High-End Smart Card. AES Candidate Conference (2000)
Shin-ichi Kawamura, Masanobu Koike, Fumihiko Sano, Atsushi Shimbo
Cox-Rower Architecture for Fast Parallel Montgomery Multiplication. EUROCRYPT (2000)
Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama
Variable supply-voltage scheme for low-power high-speed CMOS digital design. IEEE J. Solid State Circuits 33 (3) (1998)
Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama
A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. IEEE J. Solid State Circuits 33 (11) (1998)
Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakurnu, Takayasu Sakurai
, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. IEEE J. Solid State Circuits 31 (11) (1996)