Variable supply-voltage scheme for low-power high-speed CMOS digital design.
Tadahiro KurodaKojiro SuzukiShinji MitaTetsuya FujitaFumiyuki YamaneFumihiko SanoAkihiko ChibaYoshinori WatanabeKoji MatsudaTakeo MaedaTakayasu SakuraiTohru FuruyamaPublished in: IEEE J. Solid State Circuits (1998)
Keyphrases
- low power
- high speed
- mixed signal
- single chip
- power consumption
- low power consumption
- low cost
- vlsi circuits
- cmos technology
- vlsi architecture
- cmos image sensor
- logic circuits
- digital signal processing
- gate array
- analog to digital converter
- ultra low power
- power dissipation
- nm technology
- wireless transmission
- multi channel
- high power
- circuit design
- power reduction
- real time
- frame rate
- image sensor
- delay insensitive
- dynamic range
- focal plane